Skip to content

NetFPGA 1G Ported Router OPED 10G

Jump to bottom Edit New page
manihatn edited this page Apr 10, 2013 · 1 revision

Name

ported_router_oped_10g

Location

contrib-projects/ported_router_oped_10g

IP Cores

Description

This section describes the mechanism for integrating existing 1G Output Port Lookup modules into the 10G pipeline. This has been achieved using two newly developed IP cores namely, AXI4-Stream to Packet Bus Bridge and AX4-Lite to Register Bus Bridge. Remainder of the section is on how to use these two bridges in a 10G design. For information on rest of the reference pipeline, visit NetFPGA 10G Reference NIC 1G.

Using the Bridges

These two libraries are tested using Output Port Lookup Modules (OPL) taken from NetFPGA-1G core library e.g. NIC, Learning CAM Switch and CAM Router. Here we provide a general guideline that will help in setting up the library.

Before starting the porting process, the NetFPGA-1G OPL module is wrapped in an EDK compliant peripheral core. This can be done using the provided sample template which contains a generic top exposing necessary Packet Bus and Register Bus interfaces. Once done, this core is integrated into the 10G desgin using the bridges.

  • Inserting AXI4-Stream and Packet Bus Bridge

    • Insert the NetFPGA-1G core in the EDK project.
    • Connect the M_PBS bus of the "AXI4-Stream to Packet Bus Bridge" to the S_PBS bus of the NetFPGA-1G core.
    • Connect the S_PBS bus of the Bridge to the M_PBS bus of the NetFPGA-1G core.
    • Connect the S_AXI bus of the Bridge to the preceding Master module in the design e.g. if you are porting an Output Port Lookup Module, you should connect it to the Input Arbiter.
    • Conncet the M_AXI bus of the Bridge to the following Slave module in the design e.g. if you are porting an Output Port Lookup Module you should connect it to the BRAM Output Queues.

  • Inserting AXI4-Lite and Register Bus Bridge

    • Connect the M_RBS bus of the "AXI4-Lite to Register Bus Bridge" to the S_RBS bus of the NetFPGA-1G core.
    • Connect the S_RBS bus of the Bridge to the M_RBS bus of the NetFPGA-1G core.
    • Connect the S_AXI bus of the Bridge to the axi_interconnect.
    • In the Master/Slave specifc settings of the axi_interconnect, check the ACLK setting as asynchronous with respect to the Bridge.

Porting the CAM Router

In this section, we describe the process of porting the NetFPGA-1G CAM router to the new 10G platform. The steps are:

  • Create a new EDK core for the NetFPGA-1G CAM router library. Replace the black-box CAM with the Virtex5 compatible CAM using the XAPP1151.

  • Insert the AXI4-Lite to Register Bus Bridge in the EDK project. Doing so will set a default address range for this block e.g. 0x76600000 to 0x7660ffff.

  • Set the parameter C_RBS_RING_SIZE to 16.

  • Hardcode the switch parameters with the following values in the defines.vh file

    1. IO_QUEUE_STAGE_NUM 'hFF

    2. IOQ_SRC_PORT_POS 16

    3. IOQ_DST_PORT_POS 48

    4. ROUTER_OP_LUT_ROUTE_TABLE_DEPTH 32

    5. ROUTER_OP_LUT_ARP_TABLE_DEPTH 32

    6. ROUTER_OP_LUT_DST_IP_FILTER_TABLE_DEPTH 32

    7. UDP_REG_ADDR_WIDTH (32-2)

    8. CPCI_NF2_DATA_WIDTH 32

    9. ROUTER_OP_LUT_REG_ADDR_WIDTH 8

    10. ROUTER_OP_LUT_BLOCK_ADDR 0

    11. ROUTER_OP_LUT_DEFAULT_MAC_0_HI 16'hcafe

    12. ROUTER_OP_LUT_DEFAULT_MAC_0_LO 32'hf00d0001

    13. ROUTER_OP_LUT_DEFAULT_MAC_1_HI 16'hcafe

    14. ROUTER_OP_LUT_DEFAULT_MAC_1_LO 32'hf00d0002

    15. ROUTER_OP_LUT_DEFAULT_MAC_2_HI 16'hcafe

    16. ROUTER_OP_LUT_DEFAULT_MAC_2_LO 32'hf00d0003

    17. ROUTER_OP_LUT_DEFAULT_MAC_3_HI 16'hcafe

    18. ROUTER_OP_LUT_DEFAULT_MAC_3_LO 32'hf00d0004

    19. ROUTER_OP_LUT_ARP_NUM_MISSES 0 (axi address = 0x76600000)

    20. ROUTER_OP_LUT_LPM_NUM_MISSES 1 (axi address = 0x76600004)

    21. ROUTER_OP_LUT_NUM_CPU_PKTS_SENT 2 (axi address = 0x76600008)

    22. ROUTER_OP_LUT_NUM_BAD_OPTS_VER 3 (axi address = 0x7660000c)

    23. ROUTER_OP_LUT_NUM_BAD_CHKSUMS 4 (axi address = 0x76600010)

    24. ROUTER_OP_LUT_NUM_BAD_TTLS 5 (axi address = 0x76600014)

    25. ROUTER_OP_LUT_NUM_NON_IP_RCVD 6 (axi address = 0x76600018)

    26. ROUTER_OP_LUT_NUM_PKTS_FORWARDED 7 (axi address = 0x7660001c)

    27. ROUTER_OP_LUT_NUM_WRONG_DEST 8 (axi address = 0x76600020)

    28. ROUTER_OP_LUT_NUM_FILTERED_PKTS 9 (axi address = 0x76600024)

    29. ROUTER_OP_LUT_MAC_0_HI 10 (axi address = 0x76600028)

    30. ROUTER_OP_LUT_MAC_0_LO 11 (axi address = 0x7660002c)

    31. ROUTER_OP_LUT_MAC_1_HI 12 (axi address = 0x76600030)

    32. ROUTER_OP_LUT_MAC_1_LO 13 (axi address = 0x76600034)

    33. ROUTER_OP_LUT_MAC_2_HI 14 (axi address = 0x76600038)

    34. ROUTER_OP_LUT_MAC_2_LO 15 (axi address = 0x7660003c)

    35. ROUTER_OP_LUT_MAC_3_HI 16 (axi address = 0x76600040)

    36. ROUTER_OP_LUT_MAC_3_LO 17 (axi address = 0x76600044)

    37. ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI 18 (axi address = 0x76600048)

    38. ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO 19 (axi address = 0x7660004c)

    39. ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP 20(axi address = 0x76600050)

    40. ROUTER_OP_LUT_ARP_TABLE_RD_ADDR 21 (axi address = 0x76600054)

    41. ROUTER_OP_LUT_ARP_TABLE_WR_ADDR 22 (axi address = 0x76600058)

    42. ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP 23 (axi address = 0x7660005c)

    43. ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK 24 (axi address = 0x76600060)

    44. ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP 25(axi address = 0x76600064)

    45. ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT 26(axi address = 0x76600068)

    46. ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR 27 (axi address = 0x7660006c)

    47. ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR 28 (axi address = 0x76600070)

    48. ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP 29(axi address = 0x76600074)

    49. ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR 30 (axi address = 0x76600078)

    50. ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR 31 (axi address = 0x7660007c)

  • include "defines.vh" file in all 1G modules.

  • Connect the M_RBS bus of the "AXI4-Lite to Register Bus Bridge" to the S_RBS bus of the NetFPGA-1G core.

  • Connect the S_RBS bus of the Bridge to the M_RBS bus of the NetFPGA-1G core.

  • Connect the S_AXI bus of the Bridge to the axi_interconnect.

  • In the Master/Slave specifc settings of the axi_interconnect, check the ACLK setting as asynchronous with respect to the "AXI4-Lite to Register Bus Bridge".

  • Insert the "AXI4-Stream to Packet Bus Bridge" in the EDK project.

  • Connect the M_PBS bus of the "AXI4-Stream to Packet Bus Bridge" to the S_PBS bus of the NetFPGA-1G core.

  • Connect the S_PBS bus of the Bridge to the M_PBS bus of the NetFPGA-1G core.

Block Diagram

Software Plane

Three are the main software utilities provided with the router:

  • CLI (Command Line Interface, useful to manage ARP table and Forwarding Table).
  • Router Kit Daemon (simple approach to providing hardware acceleration to an unmodified Linux system) - for more information, refer to : Router Kit Daemon Web Page
  • SCONE (Software Component of NetFPGA, a user level router that performs IPv4 forwarding) - for more information, refer to: SCONE Web Page

Functional Testing

After configuring the system as explained above, functional tests were performed in order to validate the system. For the Datapath, system operates as a CAM Router. The status registers are read and verified using the driver_ctrl utility provided with the NetFPGA-10G reference NIC 10G device driver.

It's worth noticing that using this porting mechanism, the obtained router is faster than when ran on the existing NetFPGA-1G platform but is not fully 10G compatible.

Add a custom footer
Add a custom sidebar
Clone this wiki locally