Port an AXI IP to Virtex 5 device

This document describes how to import an AXI IP (shipped with Xilinx EDK 12.3 and onwards) to Virtex-5 device. Please refer to "UG642 Platform Specification Format Reference Manual" first if you are new to EDK.

1. Copy the IP core folder to the Xilinx pcore folder in the lib/hw/std/pcores directory
2. Add the virtex5tx to the option ARCH_SUPPORT_MAP = ( virtex5tx=PRODUCTION,...) in the MPD file
3. If the pcore includes the IPIF library, change the IPIF library in the HDL and pao files to "axi_lite_ipif_v1_00_a". The Xilinx IPIF is modified for XST to synthesize it under Virtex-5 architecture, changes are made in address_decoder.vhd .
4. Some encrypted cores, such as AXI interconnect, must be synthesized under Virtex-6 first, and then translate to Virtex-5 NGD.

If you fully understand what we are talking about in the above four steps, you could stop reading now. That's it. Otherwise, we will explain what we are trying to do.

First two steps are just to make IP local. We did not use Xilinx's "Make IP Local" utility since it will make a separate copy of shared pcores such as axi_lite_ipif, which has a Virtex-5 specific bug and we need to fix it later. Modifying MPD will allow EDK to synthesize the pcore on Virtex-5, instead of originally designed Virtex-6. In theory, you will be able to synthesize an IP target on Virtex-5 TX240T now.

However, the world is complicated. Xilinx XST has a different way of synthesizing for Virtex-5 and Virtex-6, even on the same HDL, which means the results are different. Specifically, a file in Xilinx axi_lite_ipif pcore (address_decoder.vhd) will fail synthesizing if you force XST to do it for Virtex-5. This file is fixed by NetFPGA-10G group. Please do a diff on this file against the original one to see what has changed (just 2 lines).

Last, we found AXI Interconnect is encrypted and fail Virtex-5 synthesis. We cannot change the HDL as we did for axi_lite_ipif. Fortunately, AXI interconnect does not have any Virtex-6 specific primitives. So in the Hardware Makefile, we play a small trick by copying an Virtex-6 SCR to the synthesis folder overriding the EDK generated SCR. After synthesizing, we use normal Virtex-5 flow for translation (ngdbuild) and the rest. You may ask why not just use Virtex-6 for the entire design flow until ngdbuild. The reason is that it will generate a lot of Virtex-6 specific primitives in the netlist (NGC) preventing ngdbuild to continue.

After all, the above hacks work for Xilinx EDK 12.3 at the time of writing. Although we plan to stay up-to-date with the latest tool versions, we do not guarantee in any way that it will continue to work in the future EDK releases. Also, since we do not change functionalities of these Xilinx pcores, you should find the documentation from Xilinx website and treat them as Xilinx pcores as opposed to NetFPGA-10G pcores (Following the Xilinx license for these cores).