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Arp Reply
nf10_arp_reply
v1.00a
Yilong Geng (Stanford University)
pcore (HW)
netfpga-10g/lib/hw/contrib/pcores/nf10_arp_reply_v1_00_a/
AXI4-Stream & AXI4-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
S_AXI: AXI4-Lite configuration register bus
C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.
C_AXIS_TUSER_WIDTH: Data width of the TUSER field.
SRC_PORT_POS: The position of the Source_Port field in TUSER.
DST_PORT_POS: The position of the Destination_Port field in TUSER.
Y = 0,1,2,3 represents 4 groups of IP-MAC address pairs.
Base Address+
0xY0: 32-bit IP address
0xY1: The lower 32 bits of the MAC address
0xY2: The higher 16 bits of the MAC address
This module is a part of the tunneling Openflow switch data path. It makes the tunnel transparent to ARP protocol.