NetFPGA 10G 1G Ethernet Interface Loopback Test

Name

loopback_test_1g

Location

projects/loopback_test_1g

IP Cores

• NetFPGA-10G Specific cores
  • nf10_1g_interface
  • nf10_mdio
  • nf10_axis_gen_check
  • OPED
• Xilinx AXI Peripheral
  • axi_interconnect
  • axi_uartlite
  • axi_timebase_wdt
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator
• Other
  • diff_input_buf

Description

This example project shows the usage of the 1G Ethernet interface on NetFPGA-10G board. Outside the FPGA, the interfaces are paired up using CAT-5/CAT-6 Ethernet cables. Inside the FPGA, two packet generator/checkers are connected to two out of the four 1G interfaces while the remaining two interfaces are looped back together. MicroBlaze subsystem will poll the statistics out of the packet generator/checkers and output them through the UART interface.

Usage

1. Build the bitfile. Please read the README under projects/loopback_test_1g/ for detailed instructions. This process will take up to an hour. However, you may skip this step if you have a pre-built bitfile available.
2. Connect Port 0 to Port 1, and Port 2 and Port 3 on the NetFPGA-10G board using CAT-5/CAT-6 Ethernet cables. You will need a SFP-CAT5 converter. A list of converters we tested is here.
3. Connect UART to the serial port (RS232) on your PC. Open a terminal (PuTTY on Windows or minicom/gtkterm on Linux) and listen to your serial port.
4. Download the bitfile to the FPGA and follow the instructions on the terminal (see the screenshot below).

Block Diagram