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AXI4 Stream Generator and Checker
nf10_axis_gen_check
v1.00a
pcore (HW)
netfpga-10g/lib/hw/std/pcores/nf10_axis_gen_check_v1_00_a/
AXI4-Stream
AXI4-lite
M_AXIS: Master AXI4-Stream bus, 8bit, 64bit or 256bit
S_AXIS: Slave AXI4-Stream bus, 8bit, 64bit or 256bit
S_AXI: Slave AXI4-Lite interface for control and status
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream bus
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream bus
C_IFG_SIZE: Size of the interframe gap between transmitted packets
C_GEN_PKT_SIZE: Size of the to be generated packet
C_CHECK_PKT_SIZE: Size of the to be checked packet
C_BASE_ADDRESS: This is the base address for the registers that can be read out over AXI-lite.
C_HIGH_ADDRESS: This is the highest address within this module that can be read out over AXI-lite.
0x0: count of transmitted packets
0x1: count of correctly received and checked packets
0x2: count of packets received with errors (This counter might be unequal 0 after the links have been established.)
0x3: reset the packet generator/checker, active high (1 for reset)
This core contains a simple AXI4 stream generator and checker. The generator transmits a hardcoded packet continously. The size of the packet and the interframe gap can be setup through parameter settings. The packet itself is hardcoded in the source and can be altered to fit the end-users requirements. It currently shifts the data over word-width boundaries to generate a pattern. The checker compares a received packet of a defined size (through parameters) against a hard-coded version. As with the generated packet, the packet is defined in the source file. Statistics can be read via an AXI4-lite interface. Available are transmit counts, receive counts and error counts.
Currently the generator generates bit-wise shifted pattern. No valid packet pattern and/or higher layer structure is programmed.
The registers can be read/write using Xil_In32 and Xil_Out32. Here is an example:
value = Xil_In32(XPAR_NF10_AXIS_GEN_CHECK_0_BASEADDR+0x0);
Xil_Out32(XPAR_NF10_AXIS_GEN_CHECK_0_BASEADDR+0x3, 0x1);
For complete examples, please refer to the embedded software of the loopback_test project.