Minor Release v2.53.0

Pull Requests Since v2.52.1

Bug

1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Enhancement

1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Unlabeled

1. #1219 - Adding SACI Version 2
2. #1209 - added RoCEv2 README

Pull Request Details

Bug Fixes and Enhancements from LDMX Project Development

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 5 10:28:09 2024 -0600
Pull:	#1166 (1899 additions, 246 deletions, 40 files changed)
Branch:	slaclab/ldmx-dev
Labels:	bug, enhancement

Notes:

Description

There are many small changes, mostly to fix issues found in simulation.

Details

• AxiStreamResize
  • Better error reporting if generic assert fails
• Ad9249ReadoutGroup2
  • Initialize signal to avoid unknowns in simulation
• Ad9249Group (simulation)
  • Fix incomplete sensitivity list
• Pgp2FcAxi
  • Apply TX FC bus from input to PGP block
• PGP2FC GTY IP Core
  • Remove "project_parameters" from XCI file
  • Allows XCI to load with different US+ FPGAs
• PGP2FC GTY IP Core Wrapper
  • Output rxPmaResetDone
    • Needed for external MMCM reset
  • Update resets based on simulation discoveries
  • Set freerun frequency to 185.71/2 MHz
• Add GTH IP Core and wrapper for PGP2FC
• ClockManagerUltraScale (Plus)
  • Resolve unknowns on DrpDo output from GT to zeros to avoid propagating them in simulation
• GtRxAlignCheck
  • Use registered values for read-only AXI-Lite registers
  • Apply bug fix so resetErr only reset the FSM when resetDone is high
• AxiLiteRingBuffer
  • Fix bugs in Rogue Device
• Rogue Devices
  • Add several registers to the "NoConfig" group

---

added RoCEv2 README

Author:	Larry Ruckman [email protected]
Date:	Wed Dec 4 13:05:27 2024 -0600
Pull:	#1209 (362 additions, 1 deletions, 3 files changed)
Branch:	slaclab/RoCE-Readme

Notes:

Providing the RoCEv2 files with a README and a LICENSE file

Description

Added the README file to the RoCEv2 related folder. In the README I cite where the files come from, the fact that they have been generated from Bluespec SystemVerilog, the fact that they have been modified and the licensing conditions

---

Adding SACI Version 2

Author:	Larry Ruckman [email protected]
Date:	Thu Dec 5 10:57:17 2024 -0600
Pull:	#1219 (1263 additions, 7 deletions, 45 files changed)
Branch:	slaclab/saci2

Notes:

Description

• https://confluence.slac.stanford.edu/x/y3TDHw

---

Patch Release v2.52.1

Description

• hot fix for conda CI build

Full Changelog: v2.52.0...v2.52.1

Minor Release v2.52.0

Pull Requests Since v2.51.0

Bug

1. #1218 - Added strWrite() procedure to declaration section of TextUtilPkg

Unlabeled

1. #1192 - Adding RoCEv2 support to the SURF Ethernet library
2. #1212 - Big fixes for SgmiiDp83867LvdsUltraScale and Ultrascale+ operations
3. #1216 - AxiStreamGearbox mod for Synopsys synth tool
4. #1213 - CXPoF: TID VHDL Style Fix
5. #1214 - Update to AxiStreamFrameRateLimiter.vhd
6. #1207 - Hot Fix for CI: Removing C++ linter
7. #1210 - Update ruckus.tcl with missing ad5541 load

Pull Request Details

Adding RoCEv2 support to the SURF Ethernet library

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 14 09:51:41 2024 -0700
Pull:	#1192 (69758 additions, 42 deletions, 108 files changed)
Branch:	slaclab/EthMacCore-RoCEv2

Notes:

Description

• migrating RoCEv2 src code from FilMarini:surf:roce
• reorg of RoCEv2 src code to EthMacRxRoCEv2.vhd & EthMacTxRoCEv2.vhd
• adding ROCEV2_EN_G generic to Ethernet lib

---

Hot Fix for CI: Removing C++ linter

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 7 14:26:59 2024 -0700
Pull:	#1207 (3 additions, 3 deletions, 1 files changed)
Branch:	slaclab/cpp-linter

Notes:

Description

• remove all the linting for now since cpplint is really only for c++ files
• We should find another linter for these pure C files

---

Update ruckus.tcl with missing ad5541 load

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 21 16:24:14 2024 -0700
Pull:	#1210 (1 additions, 0 deletions, 1 files changed)
Branch:	slaclab/ad5541-missing-ruckus-load

Notes:

Description

In the previous pull request for AD5541 one ruckus.tcl file was missed that prevents this module from being found properly.

Related

• #1172

---

Big fixes for SgmiiDp83867LvdsUltraScale and Ultrascale+ operations

Author:	Larry Ruckman [email protected]
Date:	Thu Oct 24 08:42:45 2024 -0700
Pull:	#1212 (173 additions, 134 deletions, 8 files changed)
Branch:	slaclab/GigEthLvdsUltraScale+

Notes:

Description

• Post .DCP generation hack to make it work with both Ultrascale and Ultrascale+
• exposing JUMBO_G generic at Sgmii88E1111LvdsUltraScale.vhd
• bug fixes for SgmiiDp83867
• adding triMode output port support for MDIO

---

CXPoF: TID VHDL Style Fix

Author:	Larry Ruckman [email protected]
Date:	Fri Oct 25 08:07:07 2024 -0700
Pull:	#1213 (18 additions, 18 deletions, 7 files changed)
Branch:	slaclab/CXPoF

Notes:

Description

• generics should end in '_G' and not '_C'

---

Update to AxiStreamFrameRateLimiter.vhd

Author:	Larry Ruckman [email protected]
Date:	Mon Oct 28 08:08:58 2024 -0700
Pull:	#1214 (12 additions, 2 deletions, 1 files changed)
Branch:	slaclab/AxiStreamFrameRateLimiter

Notes:

Description

• adding mAxisCtrl.pause support

---

AxiStreamGearbox mod for Synopsys synth tool

Author:	Larry Ruckman [email protected]
Date:	Mon Dec 2 21:29:12 2024 -0600
Pull:	#1216 (33 additions, 14 deletions, 2 files changed)
Branch:	slaclab/axiStreamGbox-asic-dev

Notes:

Synopsys tool (presto) failed to synthesize original version of this with the following error:

"Constant Value Required"

on all modified lines; obviously an issue with the slicing of the std_logic_vectors.

circumventing by performing bit-by-bit assignment

---

Added strWrite() procedure to declaration section of TextUtilPkg

Author:	Larry Ruckman [email protected]
Date:	Sun Dec 1 11:21:04 2024 -0600
Pull:	#1218 (4 additions, 1 deletions, 1 files changed)
Branch:	rbrglez/issue/1217-TextUtilPkg
Labels:	bug

Notes:

Description

In TextUtilPkg I added strWrite() to the declaration section of TextUtilPkg.

---

Minor Release v2.51.0

Pull Requests Since v2.50.0

Unlabeled

1. #1195 - adding Pgp4RxLiteLowSpeed.vhd
2. #1204 - introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment
3. #1194 - adding userCLk to SelectioDeserUltraScale.vhd
4. #1203 - _Qsfp.py Update
5. #1199 - Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd
6. #1197 - Increased range of SACI_NUM_CHIPS_G to support more than 4 chips
7. #1200 - Pgp4RxLiteLowSpeedLane.vhd Update
8. #1198 - Update RstSync.vhd

Pull Request Details

adding userCLk to SelectioDeserUltraScale.vhd

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 23 10:27:09 2024 -0700
Pull:	#1194 (27 additions, 8 deletions, 1 files changed)
Branch:	slaclab/ruckman/SelectioDeserUltraScale

Notes:

Description

• mapping CLKOUT1 to userClk, which is a useful optional clock reference

---

adding Pgp4RxLiteLowSpeed.vhd

Author:	Larry Ruckman [email protected]
Date:	Thu Sep 26 09:52:31 2024 -0700
Pull:	#1195 (803 additions, 0 deletions, 5 files changed)
Branch:	slaclab/Pgp4RxLiteLowSpeed

Notes:

Description

• Designed for receiving unidirectional PGP4-lite from ASIC using the FPGA's SelectIO (LVDS I/O)

---

Increased range of SACI_NUM_CHIPS_G to support more than 4 chips

Author:	Larry Ruckman [email protected]
Date:	Tue Oct 1 08:05:37 2024 -0700
Pull:	#1197 (7 additions, 7 deletions, 1 files changed)
Branch:	slaclab/saci_6_chip

Notes:

Description

The AxiLiteSaciMaster currently has a fixed limit of four ASICs ("chips"). This has been increased to six to work with a new readout system with that many ASICs.

Details

The new 3x2 Readout (https://confluence.slac.stanford.edu/x/eKRxG) seems to be first system to use more than four ASICs with a common SACI interfaces. There is no mention why only four chips were allowed previously. The hardware will arrive in a couple of weeks with which we can test running SACI with six chips, but from the code alone I don't see any reason why more than four would not work.

---

Update RstSync.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Sep 25 09:59:04 2024 -0700
Pull:	#1198 (5 additions, 2 deletions, 1 files changed)
Branch:	slaclab/RstSync-std_logic

Notes:

Description

• Using "std_logic" instead of "sl" for generics due to issues with SystemVerilog handling VHDL subtype on generics properly

---

Updates to AxiLiteSaciMaster.vhd & SaciMaster2.vhd

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 27 12:31:21 2024 -0700
Pull:	#1199 (22 additions, 8 deletions, 2 files changed)
Branch:	slaclab/AxiLiteSaciMaster-asicRstL-aware

Notes:

Description

• adding support to run SACI clock when asicRstL asserted in SACI_CLK_FREERUN_G=false mode

---

Pgp4RxLiteLowSpeedLane.vhd Update

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 30 09:13:03 2024 -0700
Pull:	#1200 (7 additions, 2 deletions, 1 files changed)
Branch:	slaclab/Pgp4RxLiteLowSpeedLane

Notes:

Description

• Mask off the Valid to the RX protocol until the gearbox is locked

---

_Qsfp.py Update

Author:	Larry Ruckman [email protected]
Date:	Wed Oct 2 11:03:34 2024 -0700
Pull:	#1203 (31 additions, 0 deletions, 1 files changed)
Branch:	slaclab/Qsfp-TxDisable

Notes:

Description

• adding TxDisable register
• adding PowerOverride & PowerMode registers

---

introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment

Author:	Larry Ruckman [email protected]
Date:	Tue Oct 1 19:27:41 2024 -0700
Pull:	#1204 (164 additions, 121 deletions, 15 files changed)
Branch:	slaclab/pgp4lite-rstPolarity

Notes:

introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to prepare for asic deployment

(ASIC designs usually employ an active-LOW reset/i.e. a rstN/enable signal)

add RST_POLARITY_G to all modules.

note that I also added RST_POLARITY_G to RX-related modules because I use them in my local behavioral simulation (no receiver in ASICs are foreseen). Since the RST_POLARITY_G generic default values are consistent, the changes in the TX/RX modules hopefully should not have impact on existing designs.

---

Patch Release v2.43.1 for SMURF

Description

• cherry picking the surf AxiStreamFifoV2 changes up to v2.50.0

Full Changelog: v2.43.0...v2.43.1

Patch Release v2.11.3 for SMURF

Description

• upgrading to [email protected] for AxiStreamFifoV2 bug fixes

Full Changelog: v2.11.2...v2.11.3

Minor Release v2.50.0

Pull Requests Since v2.49.0

Unlabeled

1. #1176 - Clean up of ethernet before adding RoCEv2 support
2. #1163 - Create SaciAxiLiteMaster module
3. #1184 - Adding AxiStreamCompact.vhd
4. #1187 - Adding AxiStreamTrailerRemove
5. #1185 - Adding AxiStreamTrailerAppend
6. #1190 - AxiStreamCompact Patch
7. #1183 - bug fix for locked IPs in MicroblazeBasicCore.bd for v2022.2 (or later)
8. #1188 - UdpEngineRx.vhd Update for RoCEv2 support
9. #1181 - pgp2fc/gtyUltraScale+/ruckus.tcl: bug fix for Vivado version checking
10. #1186 - Add some AxiVersion Rogue Device Variables to NoConfig group

Pull Request Details

Create SaciAxiLiteMaster module

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 6 07:31:54 2024 -0700
Pull:	#1163 (650 additions, 0 deletions, 5 files changed)
Branch:	slaclab/SaciAxiLiteMaster

Notes:

Description

Add a new SaciAxiLiteMaster module. This module is intended to be paired with AxiLiteSaciMaster. Together they create a an AXI-Lite bridge between two chips carried over the SACI bus.

Details

Only 20 bits of AXI-Lite address space are available, due to the limited address bits on the SACI bus protocol.

Also added a cocotb testbench for the new module.

---

Clean up of ethernet before adding RoCEv2 support

Author:	Larry Ruckman [email protected]
Date:	Mon Aug 12 08:43:30 2024 -0700
Pull:	#1176 (545 additions, 1440 deletions, 19 files changed)
Branch:	slaclab/eth-vlan-removal

Notes:

Description

• depreciating VLAN support in ethernet/EthMacCore because never tested and never used+
• depreciating VLAN support in ethernet/IpV4Engine because never tested and never used

---

pgp2fc/gtyUltraScale+/ruckus.tcl: bug fix for Vivado version checking

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 24 09:49:05 2024 -0700
Pull:	#1181 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/pgp2fc-version-check

Notes:

Description

• Pgp2fcGtyCore was build with 2023.1 (not 2020.1)

---

bug fix for locked IPs in MicroblazeBasicCore.bd for v2022.2 (or later)

Author:	Larry Ruckman [email protected]
Date:	Thu Aug 15 11:07:44 2024 -0700
Pull:	#1183 (8 additions, 6 deletions, 1 files changed)
Branch:	slaclab/microblaze-dev

Notes:

Description

• This is mostly a bug in the Vivado IP integrator when the .bd is generated from a different FPGA fabric/target
• This "upgrade" is not changing the IP's revision number but updating that metadata of the FPGA fabric from the .bd file

---

Adding AxiStreamCompact.vhd

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 6 07:26:47 2024 -0700
Pull:	#1184 (265 additions, 0 deletions, 1 files changed)
Branch:	slaclab/AxiStreamCompact

Notes:

Description

• Copied src from FilMarini:surf:roce fork (Credit to @FilMarini)
  • Required for future RoCEv2 support
• emacs VHDL beautify
• removing isRoCE port (application specific) and switch to standard reset convention

---

Adding AxiStreamTrailerAppend

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 6 07:26:26 2024 -0700
Pull:	#1185 (159 additions, 0 deletions, 1 files changed)
Branch:	slaclab/AxiStreamTrailerAppend

Notes:

Description

• Copied src from FilMarini:surf:roce fork (Credit to @FilMarini)
  • Required for future RoCEv2 support
• emacs VHDL beautify
• removing isRoCE port (application specific) and switch to standard reset convention

---

Add some AxiVersion Rogue Device Variables to NoConfig group

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 6 07:34:45 2024 -0700
Pull:	#1186 (2 additions, 0 deletions, 1 files changed)
Branch:	slaclab/axi-version-noconfig

Notes:

Description

FpgaReloatHalt and UserReset have been added to the "NoConfig" group. There is no reason these should be in a configuration YAML file.

---

Adding AxiStreamTrailerRemove

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 9 08:16:46 2024 -0700
Pull:	#1187 (177 additions, 0 deletions, 1 files changed)
Branch:	slaclab/AxiStreamTrailerRemove

Notes:

Description

• copying src from FilMarini:surf:roce fork
• emacs VHDL beautify
• switch to standard reset convention

---

UdpEngineRx.vhd Update for RoCEv2 support

Author:	Larry Ruckman [email protected]
Date:	Fri Sep 6 15:57:35 2024 -0700
Pull:	#1188 (4 additions, 0 deletions, 1 files changed)
Branch:	slaclab/UdpEngineRx-RoCEv2

Notes:

Description

• Remove 4 bytes (iCRC) from byteCnt if RoCEv2 detected

---

AxiStreamCompact Patch

Author:	Larry Ruckman [email protected]
Date:	Mon Sep 9 08:17:55 2024 -0700
Pull:	#1190 (31 additions, 30 deletions, 1 files changed)
Branch:	FilMarini/pre-release

Notes:

Applied patch to AxiStreamCompact module + SLAC emacs beautify

---

Minor Release v2.49.0

Pull Requests Since v2.48.1

Unlabeled

1. #1174 - General C/C++ Updates
2. #1170 - Adding rssi_network_analyzer.py
3. #1172 - Create AD5541 DAC
4. #1177 - Update DmaXvcWrapper.vhd
5. #1179 - _LeapXcvrUpperPages.py bug fix
6. #1173 - bug fix for SsiPrbsRx.WordRate
7. #1178 - Update PgpXvcWrapper.vhd

Pull Request Details

Adding rssi_network_analyzer.py

Author:	Larry Ruckman [email protected]
Date:	Mon Jun 24 16:34:48 2024 -0700
Pull:	#1170 (286 additions, 0 deletions, 1 files changed)
Branch:	slaclab/rssi_crash

Notes:

Description

• script used for debugging RSSI network traffic

---

Create AD5541 DAC

Author:	Larry Ruckman [email protected]
Date:	Fri Jul 5 15:33:18 2024 -0700
Pull:	#1172 (91 additions, 116 deletions, 4 files changed)
Branch:	slaclab/ad5541-dac

Notes:

Description

Created AD5541 DAC VHDL module and updated Python class to match.

Details

Created a new AxiAd5541Core VHDL module that is mostly a wrapper around a AxiSpiMaster with some generics set correctly to work with this device.

There is already a Ad5541 Python class defined in surf, which was created in 2019, but the corresponding VHLD module seems to have been forgotten. This existing Python class has different RemoteVariable related to various debug features and I/O control of the missing HDL module. Since this module already exists in surf there might be some conflict in replacing it with this new simplified version. Would it be better to try and find the missing HDL module?

JIRA

Related

---

bug fix for SsiPrbsRx.WordRate

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 10 09:05:41 2024 -0700
Pull:	#1173 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/SsiPrbsRx-patch

Notes:

Description

• LinkVariable function to be called should be get() [not read()]

---

General C/C++ Updates

Author:	Larry Ruckman [email protected]
Date:	Wed Jul 10 09:15:37 2024 -0700
Pull:	#1174 (1463 additions, 120081 deletions, 36 files changed)
Branch:	slaclab/cpplinter

Notes:

Description

• Improves the code quality by running the linter automatically for every commit via Github action
• removing xvcSrv (depreciated)
  • Users should use rogue.protocols.xilinx.Xvc instead at this point
• removing base/general/simlink's VhpiGeneric.c/.h because redundant and obsolete with respect to axi/simlink/src/VhpiGeneric.c/.h
• adding *.so to .gitignore

---

Update DmaXvcWrapper.vhd

Author:	Larry Ruckman [email protected]
Date:	Thu Jul 11 13:55:40 2024 -0700
Pull:	#1177 (60 additions, 72 deletions, 2 files changed)
Branch:	slaclab/ruck314-patch-1

Notes:

Description

• AXIS_CLK_FREQ_G is misleading name because generic is associated with the xvcClk (not axisClk) at surf.UdpDebugBridgeWrapper
• Renaming this generic to XVC_CLK_FREQ_G
• VALID_THOLD_G => 0, -- 0 = only when frame ready is required to fix the issue when there are tValid gaps in the transfer
  • https://jira.slac.stanford.edu/browse/ESROGUE-671

---

Update PgpXvcWrapper.vhd

Author:	Larry Ruckman [email protected]
Date:	Thu Jul 11 14:08:22 2024 -0700
Pull:	#1178 (1 additions, 0 deletions, 1 files changed)
Branch:	slaclab/PgpXvcWrapper-patch

Notes:

Description

• corner case bug fix to prevent a tValid gap for frames inbound to XVC

---

_LeapXcvrUpperPages.py bug fix

Author:	Larry Ruckman [email protected]
Date:	Tue Jul 23 09:49:07 2024 -0700
Pull:	#1179 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/LeapXcvr-bug-fixes

Notes:

Description

• it should be (read=read) not (read=read)()

---

v2.4.1 - SMURF Production Release

Description

• Tagging this branch since stable for smurf production
• Based on the 512fft-tkid development branch

What's Changed

• SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd by @ruck314 in #661
• Add register verify for the read/write registers by @ruck314 in #664
• Adding AxiStreamResizeTb.vhd by @ruck314 in #665
• Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd by @leosap in #662
• Resolving double YAML load issue by @ruck314 in #666
• Update _Lmk04828.py by @ruck314 in #667

Full Changelog: v2.4.0...v2.4.1

v0.0.0 - SVN state

Description

• From 7 years ago, this was the "state" of the SVN before migrating to GIT