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Merge pull request #1220 from slaclab/pre-release
Release Candidate v2.53.0
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@FilMarini: Please write up some text about how these modules were auto-generated from BlueRdma | ||
# Hardware Implementation of RoCEv2 Engine | ||
This folder contains files generated from Bluespec SystemVerilog (BSV) source code located in different repositories: [blue-rdma](https://github.com/datenlord/blue-rdma), [blue-crc](https://github.com/datenlord/blue-crc) | ||
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## Description | ||
The verilog files in the `blue-rdma` and `blue-crc` folders represent a hardware implementation of the RoCEv2 engine and a iCRC calculation engine, respectively. | ||
These files have been generated from a modified version of the BSV sources. The forked repo with the modifed version can be found [here](https://github.com/FilMarini/blue-rdma) | ||
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The modifications consists in: | ||
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* **Receiving Path Removed**: The RoCEv2 engine's receiving path as well as support for RDMA-Read operations has been entirely removed. | ||
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* **Resource Optimization**: By removing the receiving path, the core now consumes fewer hardware resources, allowing it to fit on smaller FPGAs. | ||
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* **Fixed settings**: the generated verilog has support for 1 PD, 1 QP, 2 CQ and 2 MR, in order to be as light as possible. To change these settings, the core needs to be re-generated from its original or modified repo | ||
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## License information | ||
The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders. | ||
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Please ensure compliance with both licenses when using or modifying these files. |
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These files are taken from the [B-Lang-org/bsc](https://github.com/B-Lang-org/bsc) repo. | ||
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The license file from the original repo applies to the files in this folder |
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