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Minor Release v2.53.0

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@ruck314 ruck314 released this 06 Dec 16:37
v2.53.0
60065b6
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Pull Requests Since v2.52.1

Bug

  1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Enhancement

  1. #1166 - Bug Fixes and Enhancements from LDMX Project Development

Unlabeled

  1. #1219 - Adding SACI Version 2
  2. #1209 - added RoCEv2 README

Pull Request Details

Bug Fixes and Enhancements from LDMX Project Development
Author: Larry Ruckman [email protected]
Date: Thu Dec 5 10:28:09 2024 -0600
Pull: #1166 (1899 additions, 246 deletions, 40 files changed)
Branch: slaclab/ldmx-dev
Labels: bug, enhancement

Notes:

Description

There are many small changes, mostly to fix issues found in simulation.

Details

  • AxiStreamResize
    • Better error reporting if generic assert fails
  • Ad9249ReadoutGroup2
    • Initialize signal to avoid unknowns in simulation
  • Ad9249Group (simulation)
    • Fix incomplete sensitivity list
  • Pgp2FcAxi
    • Apply TX FC bus from input to PGP block
  • PGP2FC GTY IP Core
    • Remove "project_parameters" from XCI file
    • Allows XCI to load with different US+ FPGAs
  • PGP2FC GTY IP Core Wrapper
    • Output rxPmaResetDone
      • Needed for external MMCM reset
    • Update resets based on simulation discoveries
    • Set freerun frequency to 185.71/2 MHz
  • Add GTH IP Core and wrapper for PGP2FC
  • ClockManagerUltraScale (Plus)
    • Resolve unknowns on DrpDo output from GT to zeros to avoid propagating them in simulation
  • GtRxAlignCheck
    • Use registered values for read-only AXI-Lite registers
    • Apply bug fix so resetErr only reset the FSM when resetDone is high
  • AxiLiteRingBuffer
    • Fix bugs in Rogue Device
  • Rogue Devices
    • Add several registers to the "NoConfig" group

added RoCEv2 README
Author: Larry Ruckman [email protected]
Date: Wed Dec 4 13:05:27 2024 -0600
Pull: #1209 (362 additions, 1 deletions, 3 files changed)
Branch: slaclab/RoCE-Readme

Notes:

Providing the RoCEv2 files with a README and a LICENSE file

Description

Added the README file to the RoCEv2 related folder. In the README I cite where the files come from, the fact that they have been generated from Bluespec SystemVerilog, the fact that they have been modified and the licensing conditions

Adding SACI Version 2
Author: Larry Ruckman [email protected]
Date: Thu Dec 5 10:57:17 2024 -0600
Pull: #1219 (1263 additions, 7 deletions, 45 files changed)
Branch: slaclab/saci2

Notes:

Description

Assets 2
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