RocketTile

A simple instance of a RockeTile with an example RoCC accelerator.

This project uses playground as a library. playground and this project directories should be at the same level, as shown below.

  workspace
  |-- playground
  |-- RocketTile

Make sure that you have a working playground project before proceeding further. Do not rename/modify playground directory structure.

Clone the code

git clone --recursive [email protected]:morphingmachines/RocketTile.git

Generating Verilog

Verilog code can be generated from Chisel by using the rtl Makefile target.

make rtl

The output verilog files are generated in the ./generated_sv_dir directory. This also generates a graphml file that visualizes the diplomacy graph of different components in the system. To view graphml file, as shown below, use yEd.

Simulator

To run simulations, you need to install the following dependencies

We assume Spike RISC-V ISA Simulator is installed and RISC-V environment variable is set to the Spike install path. The test bench setup uses Front-End Server (FESVR), a C++ library that manages communication between a host machine and a RISC-V DUT, which is part of the Spike build.

• The simulator executable can be generated using make verilate.

make verilate

This will generate an executable generated_sv_dir/ce.sim.SimDUT/obj_dir/VTestHarness, that can take an elf file and generate an instruction execution trace.

More targets can be listed by running make

Sanity check with bare-metal examples

src/main/resources/baremetal includes example programs (vecAdd, rocc-example, assembly-example) that can be used to run the simulation. RISCV_TESTS_SRC environment variable must be set to riscv-tests path, required for riscv_test.h file.

Run vecAdd program on the simulator

cd src/main/resources/baremetal/vecAdd
make run