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Verilator

  • Follow this link for detailed instructions.
  • Install Verilator using Run-in-Place from VERILATOR_ROOT installation option.
git clone https://github.com/verilator/verilator 
cd verilator
git tag                     # See what versions exit
#git checkout stable        # Use most recent release
#git checkout v{version}    # Switch to specified release version

autoconf # create ./configure script

export VERILATOR_ROOT=`pwd`
./configure
make -j$(nproc)

Add $VERILATOR_ROOT/bin to PATH environment variable.

Rocket-tools

We need the following software tools to run bare-metal examples on the RTL simulator.

  • RISC-V GNU Cross Compiler
  • Front-End Server (FESVR), a C++ library that manages communication between a host machine and a RISC-V DUT, that is part of the spike build.
  • riscv-tests, required for the start-up code for the baremetal environment.

For the pre-requisite list of OS-specific packages, refer to this link

Follow the steps to install the required software tools.

git clone https://github.com/chipsalliance/rocket-tools.git
cd rocket-tools
git checkout <commit>
  • Set RISCV environment variable to the install path.
export RISCV=`pwd`/../rocket-tools-install/
  • Install spike
git submodule update --recursive --init riscv-isa-sim
cd riscv-isa-sim
mkdir build
cd build
../configure --prefix=$RISCV
make -j$(nproc)
make install
  • Install RISC-V GNU cross compiler with newlib from sources. This takes some time.
git submodule update --recursive --init riscv-gnu-toolchain
cd riscv-gnu-toolchain
mkdir build
../configure --prefix=$RISCV --with-arch=rv32imf --with-abi=ilp32
#../configure --prefix=$RISCV --with-arch=rv64imfd --with-abi=lp64
make -j$(nproc)
  • Clone riscv-tests and set RISCV_TESTS_SRC environment variable.
git submodule update --recursive --init riscv-tests
export RISCV_TESTS_SRC=`pwd`/riscv-tests
  • Add $RISCV/bin to PATH environment variable.