Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

This repository contains project work for the Digital Systems course. The projects cover fundamental topics of digital design including Boolean algebra, combinational logic, sequential logic, and state machine design

designed simple digital circuits using verilog