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[py] cleanups
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shish committed Apr 6, 2024
1 parent 06f63e7 commit d14fa19
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Showing 2 changed files with 16 additions and 18 deletions.
4 changes: 0 additions & 4 deletions py/setup.py
Original file line number Diff line number Diff line change
@@ -1,11 +1,7 @@
from setuptools import setup
import os

USE_MYPYC = False
if os.getenv('ROSETTABOY_USE_MYPYC', None) == '1':
USE_MYPYC = True

if USE_MYPYC:
from mypyc.build import mypycify
packages = []
ext_modules=mypycify(
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30 changes: 16 additions & 14 deletions py/src/cpu.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

# fmt: off
OP_CYCLES: t.Final[t.List[int]] = [
# 1 2 3 4 5 6 7 8 9 A B C D E F
# 1 2 3 4 5 6 7 8 9 A B C D E F
1, 3, 2, 2, 1, 1, 2, 1, 5, 2, 2, 2, 1, 1, 2, 1, # 0
0, 3, 2, 2, 1, 1, 2, 1, 3, 2, 2, 2, 1, 1, 2, 1, # 1
2, 3, 2, 2, 1, 1, 2, 1, 2, 2, 2, 2, 1, 1, 2, 1, # 2
Expand All @@ -28,7 +28,7 @@
]

OP_CB_CYCLES: t.Final[t.List[int]] = [
# 1 2 3 4 5 6 7 8 9 A B C D E F
# 1 2 3 4 5 6 7 8 9 A B C D E F
2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, # 0
2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, # 1
2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, # 2
Expand All @@ -48,7 +48,7 @@
]

OP_TYPES: t.Final[t.List[int]] = [
# 1 2 3 4 5 6 7 8 9 A B C D E F
# 1 2 3 4 5 6 7 8 9 A B C D E F
0, 2, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0, 0, 0, 1, 0, # 0
1, 2, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0, 0, 0, 1, 0, # 1
3, 2, 0, 0, 0, 0, 1, 0, 3, 0, 0, 0, 0, 0, 1, 0, # 2
Expand Down Expand Up @@ -673,7 +673,9 @@ def tick_main(self, op: int) -> None:
self.HL = (self.HL + val16) & 0xFFFF
self.FLAG_N = False

# fmt: off
case 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 | 0x49 | 0x4A | 0x4B | 0x4C | 0x4D | 0x4E | 0x4F | 0x50 | 0x51 | 0x52 | 0x53 | 0x54 | 0x55 | 0x56 | 0x57 | 0x58 | 0x59 | 0x5A | 0x5B | 0x5C | 0x5D | 0x5E | 0x5F | 0x60 | 0x61 | 0x62 | 0x63 | 0x64 | 0x65 | 0x66 | 0x67 | 0x68 | 0x69 | 0x6A | 0x6B | 0x6C | 0x6D | 0x6E | 0x6F | 0x70 | 0x71 | 0x72 | 0x73 | 0x74 | 0x75 | 0x76 | 0x77 | 0x78 | 0x79 | 0x7A | 0x7B | 0x7C | 0x7D | 0x7E | 0x7F:
# fmt: on
# LD r,r
if op == 0x76:
# FIXME: weird timing side effects
Expand Down Expand Up @@ -911,7 +913,7 @@ def tick_cb(self, op: int) -> None:
val = self.get_reg(op)
match op & 0xF8:
# RLC
case 0x00 | 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07:
case 0x00: # ... 0x07
self.FLAG_C = (val & 1 << 7) != 0
val <<= 1
if self.FLAG_C:
Expand All @@ -922,7 +924,7 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val == 0

# RRC
case 0x08 | 0x09 | 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F:
case 0x08: # ... 0x0F
self.FLAG_C = (val & 1 << 0) != 0
val >>= 1
if self.FLAG_C:
Expand All @@ -933,7 +935,7 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val == 0

# RL
case 0x10 | 0x11 | 0x12 | 0x13 | 0x14 | 0x15 | 0x16 | 0x17:
case 0x10: # ... 0x17
orig_c = self.FLAG_C
self.FLAG_C = (val & 1 << 7) != 0
val <<= 1
Expand All @@ -945,7 +947,7 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val & 0xFF == 0

# RR
case 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F:
case 0x18: # ... 0x1F
orig_c = self.FLAG_C
self.FLAG_C = (val & 1 << 0) != 0
val >>= 1
Expand All @@ -957,7 +959,7 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val == 0

# SLA
case 0x20 | 0x21 | 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27:
case 0x20: # ... 0x27
self.FLAG_C = (val & 1 << 7) != 0
val <<= 1
val &= 0xFF
Expand All @@ -966,7 +968,7 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val == 0

# SRA
case 0x28 | 0x29 | 0x2A | 0x2B | 0x2C | 0x2D | 0x2E | 0x2F:
case 0x28: # ... 0x2F
self.FLAG_C = (val & 1 << 0) != 0
val >>= 1
if val & 1 << 6 != 0:
Expand All @@ -977,35 +979,35 @@ def tick_cb(self, op: int) -> None:
self.FLAG_Z = val == 0

# SWAP
case 0x30 | 0x31 | 0x32 | 0x33 | 0x34 | 0x35 | 0x36 | 0x37:
case 0x30: # ... 0x37
val = ((val & 0xF0) >> 4) | ((val & 0x0F) << 4)
self.FLAG_C = False
self.FLAG_N = False
self.FLAG_H = False
self.FLAG_Z = val == 0

# SRL
case 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F:
case 0x38: # ... 0x3F
self.FLAG_C = (val & 1 << 0) != 0
val >>= 1
self.FLAG_N = False
self.FLAG_H = False
self.FLAG_Z = val == 0

# BIT
case 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 | 0x49 | 0x4A | 0x4B | 0x4C | 0x4D | 0x4E | 0x4F | 0x50 | 0x51 | 0x52 | 0x53 | 0x54 | 0x55 | 0x56 | 0x57 | 0x58 | 0x59 | 0x5A | 0x5B | 0x5C | 0x5D | 0x5E | 0x5F | 0x60 | 0x61 | 0x62 | 0x63 | 0x64 | 0x65 | 0x66 | 0x67 | 0x68 | 0x69 | 0x6A | 0x6B | 0x6C | 0x6D | 0x6E | 0x6F | 0x70 | 0x71 | 0x72 | 0x73 | 0x74 | 0x75 | 0x76 | 0x77 | 0x78 | 0x79 | 0x7A | 0x7B | 0x7C | 0x7D | 0x7E | 0x7F:
case 0x40 | 0x48 | 0x50 | 0x58 | 0x60 | 0x68 | 0x70 | 0x78:
bit = (op & 0b00111000) >> 3
self.FLAG_Z = (val & (1 << bit)) == 0
self.FLAG_N = False
self.FLAG_H = True

# RES
case 0x80 | 0x81 | 0x82 | 0x83 | 0x84 | 0x85 | 0x86 | 0x87 | 0x88 | 0x89 | 0x8A | 0x8B | 0x8C | 0x8D | 0x8E | 0x8F | 0x90 | 0x91 | 0x92 | 0x93 | 0x94 | 0x95 | 0x96 | 0x97 | 0x98 | 0x99 | 0x9A | 0x9B | 0x9C | 0x9D | 0x9E | 0x9F | 0xA0 | 0xA1 | 0xA2 | 0xA3 | 0xA4 | 0xA5 | 0xA6 | 0xA7 | 0xA8 | 0xA9 | 0xAA | 0xAB | 0xAC | 0xAD | 0xAE | 0xAF | 0xB0 | 0xB1 | 0xB2 | 0xB3 | 0xB4 | 0xB5 | 0xB6 | 0xB7 | 0xB8 | 0xB9 | 0xBA | 0xBB | 0xBC | 0xBD | 0xBE | 0xBF:
case 0x80 | 0x88 | 0x90 | 0x98 | 0xA0 | 0xA8 | 0xB0 | 0xB8:
bit = (op & 0b00111000) >> 3
val &= (1 << bit) ^ 0xFF

# SET
case 0xC0 | 0xC1 | 0xC2 | 0xC3 | 0xC4 | 0xC5 | 0xC6 | 0xC7 | 0xC8 | 0xC9 | 0xCA | 0xCB | 0xCC | 0xCD | 0xCE | 0xCF | 0xD0 | 0xD1 | 0xD2 | 0xD3 | 0xD4 | 0xD5 | 0xD6 | 0xD7 | 0xD8 | 0xD9 | 0xDA | 0xDB | 0xDC | 0xDD | 0xDE | 0xDF | 0xE0 | 0xE1 | 0xE2 | 0xE3 | 0xE4 | 0xE5 | 0xE6 | 0xE7 | 0xE8 | 0xE9 | 0xEA | 0xEB | 0xEC | 0xED | 0xEE | 0xEF | 0xF0 | 0xF1 | 0xF2 | 0xF3 | 0xF4 | 0xF5 | 0xF6 | 0xF7 | 0xF8 | 0xF9 | 0xFA | 0xFB | 0xFC | 0xFD | 0xFE | 0xFF:
case 0xC0 | 0xC8 | 0xD0 | 0xD8 | 0xE0 | 0xE8 | 0xF0 | 0xF8:
bit = (op & 0b00111000) >> 3
val |= 1 << bit

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