[rv_dm,sival] Fix rv_dm_mem_access_delayed_enable

The `rv_dm_mem_access` test was not working in the
`dev_rv_dm_delayed_enable` test configuration. This is because the test
was not written to handle the additional logic required for this
configuration.

To fix this, before the host side attempts to connect via JTAG, it waits
for a message ("DEBUG_MODE_ENABLED") from the device, which will
configure the RV DM to enable the late debug feature (debug mode). This
should only be available using the OTP image with the late_debug feature
enabled, in the `delayed_enable` test configuration.

Signed-off-by: Alex Jones <[email protected]>

sw/device/tests/BUILD

@@ -5072,7 +5072,7 @@ test_suite(
 [
     opentitan_test(
         name = "rv_dm_mem_access_{}".format(test_cfg["name"]),
-        srcs = ["example_test_from_flash.c"],
+        srcs = ["rv_dm_delayed_enable.c"],
         exec_env = {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
             "//hw/top_earlgrey:fpga_cw340_sival": None,
@@ -5081,14 +5081,24 @@ test_suite(
             timeout = "moderate",
             needs_jtag = True,
             otp = test_cfg["otp"],
+            rv_dm_delayed_en = test_cfg["rv_dm_delayed_en"],
             tags = [
                 "lc_{}".format(test_cfg["lc_state"]),
-            ] + (["broken"] if "delayed_enabled" in test_cfg["name"] else []),
-            test_cmd = " --rom={rom:binary}",
+            ],
+            test_cmd = """
+                --rom={rom:binary}
+                --bootstrap="{firmware}"
+                {rv_dm_delayed_en}
+            """,
             test_harness = "//sw/host/tests/chip/rv_dm:mem_access",
         ),
         deps = [
+            "//sw/device/lib/base:multibits",
+            "//sw/device/lib/dif:lc_ctrl",
+            "//sw/device/lib/dif:rv_dm",
+            "//sw/device/lib/runtime:hart",
             "//sw/device/lib/runtime:log",
+            "//sw/device/lib/testing:lc_ctrl_testutils",
             "//sw/device/lib/testing/test_framework:ottf_main",
         ],
     )

sw/host/tests/chip/rv_dm/BUILD

@@ -35,6 +35,7 @@ rust_binary(
         "//sw/host/opentitanlib/bindgen",
         "@crate_index//:anyhow",
         "@crate_index//:clap",
+        "@crate_index//:humantime",
         "@crate_index//:log",
         "@crate_index//:rand",
         "@crate_index//:rand_chacha",

sw/host/tests/chip/rv_dm/src/mem_access.rs

@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 use std::path::PathBuf;
+use std::time::Duration;
 
 use anyhow::{ensure, Result};
 use clap::Parser;
@@ -12,6 +13,7 @@ use opentitanlib::app::TransportWrapper;
 use opentitanlib::execute_test;
 use opentitanlib::io::jtag::JtagTap;
 use opentitanlib::test_utils::init::InitializeTest;
+use opentitanlib::uart::console::UartConsole;
 use opentitanlib::util::parse_int::ParseInt;
 
 use bindgen::dif;
@@ -26,9 +28,16 @@ struct Opts {
     #[arg(long)]
     rom: PathBuf,
 
+    #[arg(long)]
+    rv_dm_delayed_enable: bool,
+
     /// Seed for random number generator.
     #[arg(long, value_parser = u64::from_str)]
     seed: Option<u64>,
+
+    /// Console receive timeout.
+    #[arg(long, value_parser = humantime::parse_duration, default_value = "100s")]
+    timeout: Duration,
 }
 
 const NUM_ACCESSES_PER_REGION: usize = 32;
@@ -41,11 +50,19 @@ fn test_mem_access(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
     log::info!("Random number generator seed is {:x}", seed);
     let mut rng = rand_chacha::ChaCha12Rng::seed_from_u64(seed);
 
-    // Avoid watchdog timeout by entering bootstrap mode.
-    transport.pin_strapping("ROM_BOOTSTRAP")?.apply()?;
-
     transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?;
     transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?;
+    let uart = &*transport.uart("console")?;
+    uart.set_flow_control(true)?;
+
+    log::info!("rv_dm_delayed_enable: {}", opts.rv_dm_delayed_enable);
+    if opts.rv_dm_delayed_enable {
+        UartConsole::wait_for(uart, r"DEBUG_MODE_ENABLED", opts.timeout)?;
+    } else {
+        // Avoid watchdog timeout by entering bootstrap mode.
+        transport.pin_strapping("ROM_BOOTSTRAP")?.apply()?;
+        transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?;
+    }
 
     let jtag = &mut *opts
         .init