[AArch64] Implement FP8 SVE intrinsics for widening conversions #118123
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| Original file line number | Diff line number | Diff line change |
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| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 | ||
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX | ||
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| // RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX | ||
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| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
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| // REQUIRES: aarch64-registered-target | ||
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| #ifdef __ARM_FEATURE_SME | ||
| #include <arm_sme.h> | ||
| #else | ||
| #include <arm_sve.h> | ||
| #endif | ||
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| #ifdef SVE_OVERLOADED_FORMS | ||
| #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 | ||
| #else | ||
| #define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 | ||
| #endif | ||
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| #ifdef __ARM_FEATURE_SME | ||
| #define STREAMING __arm_streaming | ||
| #else | ||
| #define STREAMING | ||
| #endif | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt1_bf16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z20test_svcvt1_bf16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| svbfloat16_t test_svcvt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvt1_bf16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z20test_svcvt2_bf16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| svbfloat16_t test_svcvt2_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvt2_bf16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvtlt1_bf16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z22test_svcvtlt1_bf16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| svbfloat16_t test_svcvtlt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtlt1_bf16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvtlt2_bf16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z22test_svcvtlt2_bf16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x bfloat> [[TMP0]] | ||
| // | ||
| svbfloat16_t test_svcvtlt2_bf16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtlt2_bf16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvt1_f16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z19test_svcvt1_f16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| svfloat16_t test_svcvt1_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvt1_f16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvt2_f16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z19test_svcvt2_f16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| svfloat16_t test_svcvt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvt2_f16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvtlt1_f16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z21test_svcvtlt1_f16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| svfloat16_t test_svcvtlt1_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtlt1_f16,_mf8,_fpm)(zn, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svcvtlt2_f16_mf8( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z21test_svcvtlt2_f16_mf8u13__SVMfloat8_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> [[ZN]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 8 x half> [[TMP0]] | ||
| // | ||
| svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtlt2_f16,_mf8,_fpm)(zn, fpm); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| // REQUIRES: aarch64-registered-target | ||
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| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -verify -emit-llvm %s | ||
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| #include <arm_sve.h> | ||
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| void test_features(svmfloat8_t zn, fpm_t fpm) { | ||
| svcvt1_bf16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvt1_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvt2_bf16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvt2_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvtlt1_bf16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvtlt1_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvtlt2_bf16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvtlt2_bf16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvt1_f16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvt1_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvt2_f16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvt2_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvtlt1_f16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvtlt1_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| svcvtlt2_f16_mf8_fpm(zn, fpm); | ||
| // expected-error@-1 {{'svcvtlt2_f16_mf8_fpm' needs target feature (sve,sve2,fp8)|(sme,sme2,fp8)}} | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,78 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 | ||
| ; RUN: llc -mattr=+bf16,+sve2,+fp8 < %s | FileCheck %s | ||
|
There was a problem hiding this comment. nit: I'm not sure we need |
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| ; RUN: llc -mattr=+bf16,+sme2,+fp8 --force-streaming < %s | FileCheck %s | ||
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| target triple = "aarch64-linux" | ||
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| define <vscale x 8 x bfloat> @cvt1_bf16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvt1_bf16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: bf1cvt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x bfloat> %r | ||
| } | ||
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| define <vscale x 8 x bfloat> @cvt2_bf16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvt2_bf16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: bf2cvt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x bfloat> %r | ||
| } | ||
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| define <vscale x 8 x bfloat> @cvtlt1_bf16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvtlt1_bf16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: bf1cvtlt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x bfloat> %r | ||
| } | ||
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| define <vscale x 8 x bfloat> @cvtlt2_bf16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvtlt2_bf16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: bf2cvtlt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x bfloat> %r | ||
| } | ||
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| define <vscale x 8 x half> @cvt1_f16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvt1_f16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: f1cvt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x half> %r | ||
| } | ||
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| define <vscale x 8 x half> @cvt2_f16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvt2_f16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: f2cvt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x half> %r | ||
| } | ||
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| define <vscale x 8 x half> @cvtlt1_f16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvtlt1_f16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: f1cvtlt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x half> %r | ||
| } | ||
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||
| define <vscale x 8 x half> @cvtlt2_f16(<vscale x 16 x i8> %s) { | ||
| ; CHECK-LABEL: cvtlt2_f16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: f2cvtlt z0.h, z0.b | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %s) | ||
| ret <vscale x 8 x half> %r | ||
| } | ||
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Would you mind moving the
SME2_FP8_CVT_X2_Single_Intrinsicintrinics I've merged (and perhaps the fp8fscaleones) down to this section? I'll follow this convention with my in-flight patches.