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一个用Verilog实现的简单的CPU，能够运行MIPS指令集的一个简单的子集

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
CPU_1		CPU_1
README.md		README.md

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CPU_1

一个用Verilog实现的简单的CPU，能够运行MIPS指令集的一个简单的子集

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一个用Verilog实现的简单的CPU，能够运行MIPS指令集的一个简单的子集

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