Risu PPC64 fixes #1
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Signed-off-by: Víctor Colombo <[email protected]> [ferst: Ignore FPSCR[FR] for now; Rebase; ]
The current code can be used to test VSX instructions, but the lower half of the first 32 VSRs are ignored. Add risugen code to (conditionally) initialize the 128-bits of all VSX registers and C code to compare the lower 64-bits of VSRs 0-31.
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ppc64.risu
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| # format:XX3 book:I page:673 v3.0 xvcmpnedp[.] VSX Vector Compare Not Equal Double-Precision | ||
| XVCMPNEDP PPC64LE 111100 t:5 a:5 b:5 01111011 ax:1 bx:1 tx:1 | ||
| # format:XX3 book:I page:673 v3.0 xvcmpnedp[.] VSX Vector Compare Not Equal Double-Precision | ||
| XVCMPNEDPd PPC64LE 111100 t:5 a:5 b:5 11111011 ax:1 bx:1 tx:1 | ||
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So, I just noticed I sent this in this patch.
The problem with these lines is that theses instructions were removed from Power ISA. I think they were introduced in 3.0 and removed in 3.0B. Do you think we should remove them from risu?
If we remove them, I'll have to send a separated patch, because it should not be in this commit
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This is also the case for LMDX, it was present in the first version of PowerISA v3.0 but removed on PowerISA v3.0b. I think we can keep them commented out, just like we do with other instructions that cannot be tested like SC[V], TRAP, etc.
[ferst: LDMX; comment instead of removal]
ADDPCIS uses the program counter, which depends on where the image was loaded. DARN is non-deterministic by definition, we can't compare the results between executions.
Some instructions use a pair of fp registers, represented by fr*p instead of just fr* (e.g. frap, frbp). These have the special property that they have to be an even-odd pair, starting at the even one. Otherwise, the instruction is malformed This patch adds constraints to these instructions to garantee the selected registers are even. Signed-off-by: Víctor Colombo <[email protected]>
Also adds "$ra != $rb" and "$ra != 0" constraints to avoid the current limitations of reg_plus_reg and reg_plus_imm implementations.
Unlike the other VSX instructions, the TX field of LVX is not the last bit. Also, the immediate is multiplied by 16 to calculate EA.
EA is not calculated with "reg plus reg" for these instructions. Instead, RA is the base register to access up to 16 bytes, according to RB[0:7] value. Also, abuse the memory block to put a valid value in RB. -- Power ISA says that the results are "boundedly undefined" if the contents of bits 8:63 of RB are not equal to zero. I'd expect the hardware to ignore those bits, but we observed SIGSEGVs on hardware if we use just reg($ra) and let any random value in RB.
If $ra is used as one of the source registers, we'll store a value that depends on the stack pointer in the memory block. If a load instruction later reads this value, the register comparison will fail mysteriously.
Currently, write_memblock_setup initializes 10000 bytes below the stack pointer with zeros. However, reg_plus_reg and reg_plus_imm make the instruction point to $r1+32 and $r1, respectively, causing access outside the stack frame. Change write_memblock_setup to initialize the memblock with random data, and use STDU to make $r1 point to the beginning of the block at the end.
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Works for PPC64, seems to work for m68k, but still breaks ARM.
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