Green Reference Router
The Green Reference Router is a project built on top of Reference Router in order to design a "Green Router": an energy aware router. The Reference Router provides a hardware register which allows the board to switch the clock frequency between 62.5 MHz and 125 MHz. However, the original Reference Router does not allow this change at run-time and when the clock frequency is changed the board needs to update all the ARP (Address Resolution Protocol), routing tables and other important run-time data taking several seconds.
Status :Released
Version : 1.0
Authors : ***
NetFPGA base source : 2.0
- Download and install the project at the following link.
We have improved the frequency switching capabilities developing a software module (called "Download Very Fast", it can be found as "download_very_fast.c" inside the "sw" sub-directory of the green_reference_router project) which save the state of the board before restarting the board with the new clock frequency with the last previous board state. With this new functionality, the boards takes 2ms to switch the clock frequency. (Obviously, this reset time results in a QoS decrease; in particular it may cause loss of the incoming packets). From the energy point of view, we have assessed that the energy necessary to apply our switching procedure is negligible. Using this new facility we have built, the frequency switch can be performed at run-time, giving us the possibility to design a new green architecture, with frequency scaling capabilities.
We have also introduced a three hardware modules inside the User Data Path Pipeline, which are used to measure at hardware level the input and output bit rate and a software module, called Governor, implements a Control Policy to switch the clock according to the bit rate to be processed. The resulting architecture is depicted in figure. The green boxes indicate the new modules whereas the blue boxes refer to the original design.
In order to decrease energy consumption, but at the same time control the QoS maintaining it acceptable the Governor has the aim of changing the clock frequency of the CPU to avoid waste of energy when the input traffic is less than a given threshold, and at the same time, avoid as much as possible to degrade the QoS. To this purpose, it reads the run-time value of the input bit rate and decides the CPU clock frequency according to the power management policy described below:
- if the clock frequency was previously set to 62.5 MHz and the current input bit rate needs that the clock frequency has to be switched to 125 MHz, the frequency is changed in order to avoid losses due to the low processing power;
- if the clock frequency was previously set to 125 MHz and the current input bit rate could be supported by 62.5 MHz, the frequency is changed with a probability p(input_bit_rate), which depends on the current input bit rate.
The Input Bit Rate Calculator is a hardware module that provides the input bit rate which is received within the input queues from the Ethernet ports. This module computes and gives the input bit rate of each queue and the overall bit rate. Information needed to compute the input bit rate is already available within the NetFPGA registers. In particular, the number of bytes received in each input queue is accessible through the MAC_GRP_i_RX_QUEUE_NUM_BYTES_PUSHED_REG register (where i ranges in {0, …, 3} as we have four input queues). Each of the four registers contains the progressive number of bytes received in the corresponding input queue. Each register has a fixed dimension of 32 bits: when the value of the register reaches the maximum it restarts from 0. In order to compute the bit rate for the input queue i we need to read the value of the ith register each time window w and convert the number of received bytes within w in a bit rate value. In the following, a list of new defined registers to provide the bit rate to the software level.
Register Name Description INPUT_CYCLE Input register containing the time information for sampling INPUT_Q0_BITRATE Output register containing bit rate for queue 0 INPUT_Q1_BITRATE Output register containing bit rate for queue 1 INPUT_Q2_BITRATE Output register containing bit rate for queue 2 INPUT_Q3_BITRATE Output register containing bit rate for queue 3 TOTAL_INPUT_BITRATE Output register containing the total bit rate
Similarly to the Input Bit Rate Calculator module, the Output Bit Rate Calculator is a hardware module that provides the output bit rate for each Transmission queue and the overall output bit rate as well. The same concepts discussed before are applied even in this case. Moreover, the same number of registers have been defined for the output bit rate and have a similar purpose. The Output Bit Rate Calculator module receives a signal from each of the MAC output queues. This signal has the same value corresponding to the MAC_GRP_i_TX_QUEUE_NUM_BYTES_PUSHED_REG registers (for i = {0, . . . , 3} ). It counts the number of bytes that have been sent out of the Tx queues to Ethernet. The nf2_core.v, mac_grp_regs.v, and nf2_mac_grp.v modules have been slightly changed in order to forward the reg_file[MAC_GRP_TX_QUEUE_NUM_BYTES_PUSHED] signal to the User Data Path module. Therefore, defining the Output Bit Rate Calculator module within the User Data Path allowed us to capture the signals above and process them. Then we have proceeded analogously to Section 3.1 using a similar state machine architecture.
An exponentially weighted moving average (EWMA), is a type of infinite impulse response filter that applies weighting factors which decrease exponentially. The weighting for each older data point decreases exponentially, never reaching zero. We have introduced a new register, called ALPHA, which stores the value for α chosen by the user. The Bit Rate EWMA Calculator module gets an input signal from the Input Bit Rate Calculator module which corresponds to the overall input bit rate. Taking into account all the possible values in that range would have meant to complicate a lot the logic and therefore the performances of the module as floating point numbers multiplication is not standard in Verilog and requires very high CPU computational power. For such a reason, we have simplified the usual EWMA formula by using right shift and multiplication operators instead of the regular division. On the one hand, proceeding like that, we could consider only a finite number of values for α; on the other hand, these values range from 0 to 1 in steps of 0.125 and give enough choice to the user for the EWMA calculation.