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Update fallthrough_small_fifo_v2.v #11

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Update fallthrough_small_fifo_v2.v #11

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4 changes: 2 additions & 2 deletions lib/verilog/core/utils/src/fallthrough_small_fifo_v2.v
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 1998 2007-07-21 01:22:57Z grg $
//
// Module: fallthrough_small_fifo.v
// Module: fallthrough_small_fifo_v2.v
// Project: utils
// Description: small fifo with fallthrough i.e. data valid when rd is high
//
Expand All @@ -12,7 +12,7 @@
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module fallthrough_small_fifo
module fallthrough_small_fifo_v2
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1)
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