[WIP] Spi support

UefiPayloadPkg/BlSMMStoreDxe/BlSMMStoreFvbDxe.c

@@ -49,6 +49,7 @@ InitializeFvAndVariableStoreHeaders (
   IN SMMSTORE_INSTANCE *Instance
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EFI_STATUS                          Status;
   VOID*                               Headers;
   UINTN                               HeadersLength;
@@ -129,6 +130,7 @@ ValidateFvHeader (
   IN  SMMSTORE_INSTANCE *Instance
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   UINT16                      Checksum;
   EFI_FIRMWARE_VOLUME_HEADER  *FwVolHeader;
   VARIABLE_STORE_HEADER       *VariableStoreHeader;
@@ -257,6 +259,7 @@ FvbGetAttributes(
   OUT       EFI_FVB_ATTRIBUTES_2                   *Attributes
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EFI_FVB_ATTRIBUTES_2  FlashFvbAttributes;
   SMMSTORE_INSTANCE *Instance;
 
@@ -313,6 +316,7 @@ FvbSetAttributes(
   IN OUT    EFI_FVB_ATTRIBUTES_2                 *Attributes
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
   return EFI_UNSUPPORTED;
 }
@@ -341,6 +345,7 @@ FvbGetPhysicalAddress (
   OUT       EFI_PHYSICAL_ADDRESS                 *Address
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   ASSERT(Address != NULL);
 
   *Address = mFlashNvStorageVariableBase;
@@ -382,6 +387,7 @@ FvbGetBlockSize (
   OUT       UINTN                                *NumberOfBlocks
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EFI_STATUS Status;
   SMMSTORE_INSTANCE *Instance;
 
@@ -455,6 +461,7 @@ FvbRead (
   IN OUT    UINT8                                 *Buffer
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   UINTN         BlockSize;
   SMMSTORE_INSTANCE *Instance;
 
@@ -548,6 +555,7 @@ FvbWrite (
   IN        UINT8                                 *Buffer
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   UINTN         BlockSize;
   SMMSTORE_INSTANCE *Instance;
 
@@ -625,6 +633,7 @@ FvbEraseBlocks (
   ...
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EFI_STATUS  Status;
   VA_LIST     Args;
   EFI_LBA     StartingLba; // Lba from which we start erasing
@@ -731,6 +740,7 @@ FvbVirtualNotifyEvent (
   IN VOID             *Context
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
   return;
 }
@@ -741,6 +751,7 @@ SMMStoreFvbInitialize (
   IN SMMSTORE_INSTANCE* Instance
   )
 {
+  DEBUG((EFI_D_INFO, "%a\n", __FUNCTION__));
   EFI_STATUS  Status;
   UINT32      FvbNumLba;
   EFI_BOOT_MODE BootMode;

UefiPayloadPkg/SPI/FchSPICtrl.c

@@ -0,0 +1,157 @@
+#include <Include/Library/DebugLib.h>
+#include <Include/Library/PciLib.h>
+#include <Include/Library/TimerLib.h>
+#include <Include/PiDxe.h>
+#include "FchSPIUtil.h"
+#include "GenericSPI.h"
+#include "SPI.h"
+#include "spi_flash_internal.h"
+
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GRANULARITY_TEST_4k			0x0000f000		/* bits 15-12 */
+#define WORD_TO_DWORD_UPPER(x)	((x << 16) & 0xffff0000)
+
+/* SPI MMIO registers */
+#define SPI_RESTRICTED_CMD1				0x04
+#define SPI_RESTRICTED_CMD2				0x08
+#define SPI_CNTRL1								0x0c
+#define SPI_CMD_CODE							0x45
+#define SPI_CMD_TRIGGER						0x47
+#define SPI_CMD_TRIGGER_EXECUTE		0x80
+#define SPI_TX_BYTE_COUNT					0x48
+#define SPI_RX_BYTE_COUNT					0x4b
+#define SPI_STATUS								0x4c
+#define SPI_DONE_BYTE_COUNT_SHIFT	0
+#define SPI_DONE_BYTE_COUNT_MASK	0xff
+#define SPI_FIFO_WR_PTR_SHIFT			8
+#define SPI_FIFO_WR_PTR_MASK			0x7f
+#define SPI_FIFO_RD_PTR_SHIFT			16
+#define SPI_FIFO_RD_PTR_MASK			0x7f
+
+#define MAX_ROM_PROTECT_RANGES		4
+#define ROM_PROTECT_RANGE0				0x50
+#define ROM_PROTECT_RANGE_REG(n)	(ROM_PROTECT_RANGE0 + (4 * n))
+
+static int wait_for_ready(VOID)
+{
+	CONST UINT64 timeoutMilisecond = 500;
+	CONST UINT64 nanoToMiliDivider = 1000000;
+	CONST UINT64 startTimeMilisec =
+		GetTimeInNanoSecond(GetPerformanceCounter()) / nanoToMiliDivider;
+	CONST UINT64 endTimeMilisec = startTimeMilisec + timeoutMilisecond;
+	UINT64 timeNow = startTimeMilisec;
+
+	do {
+		if (!(spi_read32(SPI_STATUS) & SPI_BUSY))
+			return 0;
+		timeNow = GetTimeInNanoSecond(GetPerformanceCounter()) / nanoToMiliDivider;
+	} while (
+				timeNow<startTimeMilisec
+		|| (timeNow>startTimeMilisec && timeNow>endTimeMilisec));
+
+	return -1;
+}
+
+int execute_command(VOID)
+{
+	spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE);
+	if(wait_for_ready())
+		DEBUG((EFI_D_INFO,
+      "%a: FCH_SC Error: Timeout executing command\n", __FUNCTION__));
+
+	return 0;
+}
+
+VOID spi_init(VOID)
+{
+	spi_get_bar();
+}
+
+int spi_ctrlr_xfer(CONST struct spi_slave *slave, CONST VOID *dout,
+			__SIZE_TYPE__ bytesout, VOID *din, __SIZE_TYPE__ bytesin)
+{
+	__SIZE_TYPE__ count;
+	UINT8 cmd;
+	UINT8 *bufin = din;
+	CONST UINT8 *bufout = dout;
+
+	/* First byte is cmd which cannot be sent through FIFO */
+	cmd = bufout[0];
+	bufout++;
+	bytesout--;
+
+	/*
+	 * Check if this is a write command attempting to transfer more bytes
+	 * than the controller can handle.  Iterations for writes are not
+	 * supported here because each SPI write command needs to be preceded
+	 * and followed by other SPI commands.
+	 */
+	if (bytesout + bytesin > SPI_FIFO_DEPTH) {
+		DEBUG((EFI_D_INFO,
+      "%a: FCH_SC: Too much to transfer, code error!\n", __FUNCTION__));
+		return -1;
+	}
+
+	if (wait_for_ready())
+		return -1;
+
+	spi_write8(SPI_CMD_CODE, cmd);
+	spi_write8(SPI_TX_BYTE_COUNT, bytesout);
+	spi_write8(SPI_RX_BYTE_COUNT, bytesin);
+
+	for (count = 0; count < bytesout; count++)
+		spi_write8(SPI_FIFO + count, bufout[count]);
+
+	if (execute_command())
+		return -1;
+
+	for (count = 0; count < bytesin; count++)
+		bufin[count] = spi_read8(SPI_FIFO + count + bytesout);
+
+	return 0;
+}
+
+int xfer_vectors(CONST struct spi_slave *slave,
+			struct spi_op vectors[], __SIZE_TYPE__ count)
+{
+	return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
+}
+
+int protect_a_range(UINT32 value)
+{
+	UINT32 reg32;
+	UINT8 n;
+
+	/* find a free protection register */
+	for (n = 0; n < MAX_ROM_PROTECT_RANGES; n++) {
+		reg32 = PciRead32(
+			PCI_LIB_ADDRESS(PCU_BUS, PCU_DEV, LPC_FUNC, ROM_PROTECT_RANGE_REG(n)));
+		if (!reg32)
+			break;
+	}
+	if (n == MAX_ROM_PROTECT_RANGES)
+		return -1; /* no free range */
+
+	PciWrite32(
+		PCI_LIB_ADDRESS(PCU_BUS, PCU_DEV, LPC_FUNC, ROM_PROTECT_RANGE_REG(n)),
+		value);
+	return 0;
+}
+
+CONST struct spi_ctrlr fch_spi_flash_ctrlr = {
+	.xfer = spi_ctrlr_xfer,
+	.xfer_vector = xfer_vectors,
+	.max_xfer_size = SPI_FIFO_DEPTH,
+	.flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,
+};
+
+CONST struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{
+		.ctrlr = &fch_spi_flash_ctrlr,
+		.bus_start = 0,
+		.bus_end = 0,
+	},
+};
+
+CONST __SIZE_TYPE__ spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

UefiPayloadPkg/SPI/FchSPICtrl.h

@@ -0,0 +1,37 @@
+#ifndef FCH_SPI_CTRL_H
+#define FCH_SPI_CTRL_H
+
+#include <Include/PiDxe.h>
+#include "GenericSPI.h"
+
+union pci_bank {
+	UINT8 reg8[4096];
+	UINT16 reg16[4096 / sizeof(UINT16)];
+	UINT32 reg32[4096 / sizeof(UINT32)];
+};
+
+int execute_command(VOID);
+VOID spi_init(VOID);
+int spi_ctrlr_xfer(CONST struct spi_slave *slave, CONST VOID *dout,
+			__SIZE_TYPE__ bytesout, VOID *din, __SIZE_TYPE__ bytesin);
+int xfer_vectors(CONST struct spi_slave *slave,
+			struct spi_op vectors[], __SIZE_TYPE__ count);
+int protect_a_range(UINT32 value);
+
+/*
+ * Protect range of SPI flash defined by region using the SPI flash controller.
+ *
+ * Note: Up to 4 ranges can be protected, though if a particular region requires more than one
+ * range, total number of regions decreases accordingly. Each range can be programmed to 4KiB or
+ * 64KiB granularity.
+ *
+ * Warning: If more than 1 region needs protection, and they need mixed protections (read/write)
+ * than start with the region that requires the most protection. After the restricted commands
+ * have been written, they can't be changed (write once). So if first region is write protection
+ * and second region is read protection, it's best to define first region as read and write
+ * protection.
+ */
+int fch_spi_flash_protect(CONST struct spi_flash *flash, CONST struct region *region,
+				 CONST enum ctrlr_prot_type type);
+
+#endif /* FCH_SPI_CTRL_H */

UefiPayloadPkg/SPI/FchSPIUtil.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <Include/Library/DebugLib.h>
+#include <Include/Library/PciLib.h>
+#include <Include/PiDxe.h>
+#include <Library/IoLib.h>
+#include "FchSPICtrl.h"
+#include "FchSPIUtil.h"
+#include "SPI.h"
+
+#define _LPCB_DEV PCI_DEV(0, 0x14, 0x3)
+#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
+#define SPI_BASE_ALIGNMENT 0x00000040
+#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
+
+static UINTN spi_base = 0;
+
+UINTN lpc_get_spibase(VOID)
+{
+	UINT32 base;
+	base = PciRead32(
+		PCI_LIB_ADDRESS(PCU_BUS, PCU_DEV, LPC_FUNC, SPIROM_BASE_ADDRESS_REGISTER));
+	base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
+	return (unsigned long int)base;
+}
+
+VOID spi_set_base(UINTN base)
+{
+	spi_base = base;
+}
+
+UINTN spi_get_bar(VOID)
+{
+	if (spi_base == 0) {
+		spi_set_base(lpc_get_spibase());
+	}
+	return spi_base;
+}
+
+UINT8 spi_read8(UINT8 reg)
+{
+	return MmioRead8((spi_get_bar() + reg));
+}
+
+UINT16 spi_read16(UINT8 reg)
+{
+	return MmioRead16((spi_get_bar() + reg));
+}
+
+UINT32 spi_read32(UINT8 reg)
+{
+	return MmioRead32((spi_get_bar() + reg));
+}
+
+VOID spi_write8(UINT8 reg, UINT8 val)
+{
+	MmioWrite8((spi_get_bar() + reg), val);
+}
+
+VOID spi_write16(UINT8 reg, UINT16 val)
+{
+	MmioWrite16((spi_get_bar() + reg), val);
+}
+
+VOID spi_write32(UINT8 reg, UINT32 val)
+{
+	MmioWrite32((spi_get_bar() + reg), val);
+}

UefiPayloadPkg/SPI/FchSPIUtil.h

@@ -0,0 +1,16 @@
+#ifndef FCH_SPI_UTIL_H
+#define FCH_SPI_UTIL_H
+
+#include <Include/PiDxe.h>
+
+UINTN lpc_get_spibase(VOID);
+VOID spi_set_base(UINTN base);
+UINTN spi_get_bar(VOID);
+UINT8 spi_read8(UINT8 reg);
+UINT16 spi_read16(UINT8 reg);
+UINT32 spi_read32(UINT8 reg);
+VOID spi_write8(UINT8 reg, UINT8 val);
+VOID spi_write16(UINT8 reg, UINT16 val);
+VOID spi_write32(UINT8 reg, UINT32 val);
+
+#endif /* FCH_SPI_UTIL_H */