-
Notifications
You must be signed in to change notification settings - Fork 1
/
control_unit.v
326 lines (315 loc) · 9.33 KB
/
control_unit.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
/*
* Copyright (c) 2021, Marcos Medeiros
* Licensed under BSD 3-clause.
*/
`include "riscvdefs.vh"
module ControlUnit(
input clk,
input reset,
input [31:0] dataIn,
input [31:0] ir,
input aluFlag,
output reg writeEnable,
output reg irWriteEnable,
output reg addressIsPc,
output reg incrementPc,
output reg [1:0] regDataSrc,
output reg regWriteEnable,
output reg pcWriteEnable,
output reg [1:0] aluSrcA,
output reg [2:0] aluSrcB,
output reg [3:0] aluOperation,
output reg [1:0] readLen,
output reg [1:0] writeLen,
output reg readSignExtend
);
parameter [2:0] FETCH0 = 0;
parameter [2:0] FETCH1 = 1;
parameter [2:0] DECODE = 2;
parameter [2:0] EX1 = 3;
parameter [2:0] EX2 = 4;
parameter [2:0] EX3 = 5;
parameter [2:0] EX4 = 6;
reg [2:0] state;
wire [2:0] funct3 = ir[14:12];
wire [6:0] funct7 = ir[31:25];
wire [6:0] opcode = ir[6:0];
reg branchTestTrue = 0;
always @(posedge clk)
begin
if (reset)
begin
state <= FETCH0;
writeEnable <= 0;
regWriteEnable <= 0;
incrementPc <= 0;
addressIsPc <= 1;
aluSrcA <= `ALU_SRC_A_REG;
aluSrcB <= `ALU_SRC_B_REG;
pcWriteEnable <= 0;
readLen <= `LOAD_STORE_WORD;
writeLen <= `LOAD_STORE_WORD;
readSignExtend <= 0;
end
else
begin
if (state == FETCH0)
begin
$display("FETCH0");
writeEnable <= 0;
state <= FETCH1;
irWriteEnable <= 1;
addressIsPc <= 1;
incrementPc <= 1;
regWriteEnable <= 0;
regDataSrc <= `REG_DATA_SRC_ALU;
aluSrcA <= `ALU_SRC_A_REG;
aluSrcB <= `ALU_SRC_B_REG;
aluOperation <= `ALU_A;
pcWriteEnable <= 0;
branchTestTrue <= 0;
writeLen <= `LOAD_STORE_WORD;
readLen <= `LOAD_STORE_WORD;
readSignExtend <= 0;
end
else
if (state == FETCH1)
begin
$display("FETCH1");
state <= DECODE;
irWriteEnable <= 0;
incrementPc <= 0;
end
else
begin
$display("Execute %x", ir);
// LUI
if (opcode == 7'b0110111)
begin
$display("LUI");
aluSrcB <= `ALU_SRC_B_IMM_U_TYPE;
aluOperation <= `ALU_B;
regWriteEnable <= 1;
state <= FETCH0;
end
else
// AUIPC
if (opcode == 7'b0010111)
begin
$display("AUIPC");
aluSrcA <= `ALU_SRC_A_PREV_PC;
aluSrcB <= `ALU_SRC_B_IMM_U_TYPE;
aluOperation <= `ALU_ADD;
regWriteEnable <= 1;
pcWriteEnable <= 1;
state <= FETCH0;
end
else
// I-TYPE
if (opcode == 7'b0010011)
begin
$display("I-TYPE");
case (funct3)
3'b000: aluOperation <= `ALU_ADD;
3'b001: aluOperation <= `ALU_SLL;
3'b010: aluOperation <= `ALU_SLT;
3'b011: aluOperation <= `ALU_SLTU;
3'b100: aluOperation <= `ALU_XOR;
3'b101: aluOperation <= (funct7 == 7'h20) ? `ALU_SRA : `ALU_SRL;
3'b110: aluOperation <= `ALU_OR;
3'b111: aluOperation <= `ALU_AND;
endcase
regWriteEnable <= 1;
aluSrcB <= `ALU_SRC_B_IMM_I_TYPE;
state <= FETCH0;
end
else
// R-TYPE
if (opcode == 7'b0110011)
begin
$display("R-TYPE");
case (funct3)
3'b000: aluOperation <= (funct7 == 7'h20) ? `ALU_SUB : `ALU_ADD;
3'b001: aluOperation <= `ALU_SLL;
3'b010: aluOperation <= `ALU_SLT;
3'b011: aluOperation <= `ALU_SLTU;
3'b100: aluOperation <= `ALU_XOR;
3'b101: aluOperation <= (funct7 == 7'h20) ? `ALU_SRA : `ALU_SRL;
3'b110: aluOperation <= `ALU_OR;
3'b111: aluOperation <= `ALU_AND;
endcase
regWriteEnable <= 1;
aluSrcB <= `ALU_SRC_B_REG;
state <= FETCH0;
end
else
// B-TYPE
if (opcode == 7'b1100011)
begin
$display("B-TYPE");
if (state == DECODE)
begin
case (funct3)
3'b000: begin aluOperation <= `ALU_EQ; branchTestTrue <= 1; end // BEQ
3'b001: begin aluOperation <= `ALU_EQ; end // BNE
3'b100: begin aluOperation <= `ALU_SLT; branchTestTrue <= 1; end // BLT
3'b101: begin aluOperation <= `ALU_SLT; end // BGE
3'b110: begin aluOperation <= `ALU_SLTU; branchTestTrue <= 1; end // BLTU
3'b111: begin aluOperation <= `ALU_SLTU; end // BGEU
default: aluOperation <= `ALU_EQ;
endcase
state <= EX1;
end
else
if (state == EX1)
begin
aluSrcA <= `ALU_SRC_A_PREV_PC;
aluSrcB <= `ALU_SRC_B_IMM_B_TYPE;
aluOperation <= `ALU_ADD;
if ((branchTestTrue & aluFlag) | (~branchTestTrue & ~aluFlag))
begin
pcWriteEnable <= 1;
state <= EX2;
end
else
begin
state <= FETCH0;
end
end
else
if (state == EX2)
begin
// Delay?
pcWriteEnable <= 0;
state <= FETCH0;
end
end
else
// JAL
if (opcode == 7'b1101111)
begin
$display("JAL");
if (state == DECODE)
begin
aluSrcA <= `ALU_SRC_A_PREV_PC;
aluSrcB <= `ALU_SRC_B_IMM_J_TYPE;
aluOperation <= `ALU_ADD;
regDataSrc <= `REG_DATA_SRC_PC;
pcWriteEnable <= 1;
regWriteEnable <= 1;
state <= EX1;
end
else
begin
// Delay?
pcWriteEnable <= 0;
regWriteEnable <= 0;
state <= FETCH0;
end
end
else
// JALR
if (opcode == 7'b1100111)
begin
$display("JALR");
if (state == DECODE)
begin
aluSrcA <= `ALU_SRC_A_REG;
aluSrcB <= `ALU_SRC_B_IMM_I_TYPE;
aluOperation <= `ALU_ADD;
regDataSrc <= `REG_DATA_SRC_PC;
pcWriteEnable <= 1;
regWriteEnable <= 1;
state <= EX1;
end
else
begin
// Delay?
pcWriteEnable <= 0;
regWriteEnable <= 0;
state <= FETCH0;
end
end
else
// Loads
if (opcode == 7'b0000011)
begin
if (state == DECODE)
begin
aluSrcA <= `ALU_SRC_A_REG;
aluSrcB <= `ALU_SRC_B_IMM_I_TYPE;
aluOperation <= `ALU_ADD;
regDataSrc <= `REG_DATA_SRC_MEM;
addressIsPc <= 0;
state <= EX1;
end
else
if (state == EX1)
begin
case (funct3)
3'b000: begin readLen <= `LOAD_STORE_BYTE; readSignExtend <= 1; end
3'b001: begin readLen <= `LOAD_STORE_HALF; readSignExtend <= 1; end
3'b010: begin readLen <= `LOAD_STORE_WORD; end
3'b100: begin readLen <= `LOAD_STORE_BYTE; end
3'b101: begin readLen <= `LOAD_STORE_HALF; end
endcase
regWriteEnable <= 1;
state <= EX2;
end
else
if (state == EX2)
begin
regWriteEnable <= 0;
addressIsPc <= 1;
state <= FETCH0;
end
end
else
// Stores
if (opcode == 7'b0100011)
begin
if (state == DECODE)
begin
aluSrcA <= `ALU_SRC_A_REG;
aluSrcB <= `ALU_SRC_B_IMM_S_TYPE;
aluOperation <= `ALU_ADD;
regDataSrc <= `REG_DATA_SRC_MEM;
readLen <= `LOAD_STORE_WORD;
readSignExtend <= 0;
addressIsPc <= 0;
state <= EX1;
end
else
if (state == EX1)
begin
// Delay?
state <= EX2;
end
else
if (state == EX2)
begin
case (funct3)
3'b000: writeLen <= `LOAD_STORE_BYTE;
3'b001: writeLen <= `LOAD_STORE_HALF;
3'b010: writeLen <= `LOAD_STORE_WORD;
endcase
writeEnable <= 1;
state <= EX3;
end
else
if (state == EX3)
begin
addressIsPc <= 1;
writeEnable <= 0;
state <= FETCH0;
end
end
else
begin
$display("Error %x [%x]", ir, opcode);
state <= FETCH0;
end
end
end
end
endmodule