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RISCV_SOC.v
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RISCV_SOC.v
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//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module RISCV_SOC(
input CLOCK_50,
input [3:0] KEY,
output reg [9:0] LEDR,
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
/*wire [31:0] data;
assign HEX0 = data[7:0];
assign HEX1 = data[14:8];
assign HEX2 = data[21:15];
assign HEX3 = data[28:22];
assign HEX4 = data[31:29];*/
//soctop st(.clk(CLOCK_50), .reset(KEY[0]), .do(data));
//=======================================================
// Structural coding
//=======================================================
wire [31:0] cpuDataOut;
wire [31:0] busAddress;
wire busWriteEnable;
assign do = busAddress;
// MEMORY MAP
// 0000_0000h - 000F_FFFF ROM 1MB max
// 0010_0000h - 001F_FFFF RAM 1MB max
// 0020_0000h - 002F_FFFF VRAM 1MB max
// 8000_0000h - 8000_0FFF IO
wire ioSelect = busAddress[31];
wire gpuSelect = busAddress[21];
wire romSelect = ~busAddress[20];
wire ramSelect = busAddress[20];
wire [31:0] ramDataOut;
wire [31:0] romDataOut;
wire [31:0] gpuDataOut;
wire clk = CLOCK_50;
reg [31:0] ioDataOut;
wire [31:0] busDataIn = ioSelect ? ioDataOut :
gpuSelect ? gpuDataOut :
ramSelect ? ramDataOut :
romDataOut;
always @(posedge clk)
begin
if (ioSelect)
begin
if (busWriteEnable)
LEDR <= cpuDataOut[9:0];
else
ioDataOut <= LEDR;
end
end
GPU gpu(
.clk(clk),
.enable(gpuSelect),
.busAddress(busAddress[17:1]),
.busWriteEnable(busWriteEnable),
.busDataOut(gpuDataOut),
.busDataIn(cpuDataOut),
.VGA_B(VGA_B),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_CLK(VGA_CLK),
.VGA_G(VGA_G),
.VGA_HS(VGA_HS),
.VGA_R(VGA_R),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_VS(VGA_VS)
);
ROM rom(
.clk(clk),
.enable(romSelect),
.address({ 12'b0, busAddress[19:0] }),
.dataIn(cpuDataOut),
.dataOut(romDataOut)
);
RAM ram(
.clk(clk),
.enable(ramSelect),
.address({ 12'b0, busAddress[19:0] }),
.dataIn(cpuDataOut),
.writeEnable(busWriteEnable),
.dataOut(ramDataOut)
);
RISCV cpu(
.clk(clk),
.reset(~KEY[0]),
.dataIn(busDataIn),
.dataOut(cpuDataOut),
.address(busAddress),
.writeEnable(busWriteEnable)
);
endmodule