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mor1kx-generic.core
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mor1kx-generic.core
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CAPI=2:
name: ::mor1kx-generic:1.1
description: "Minimal mor1kx simulation environment"
filesets:
mor1kx_modules:
depend:
- mor1kx
marocchino_modules:
depend:
- or1k_marocchino
soc_files:
files:
- rtl/verilog/wb_intercon.vh: {is_include_file: true}
- rtl/verilog/orpsoc_top.v
- rtl/verilog/wb_intercon.v
file_type: verilogSource
depend:
- intgen
- adv_debug_sys
- ">=jtag_tap-1.13"
- ">=uart16550-1.5.4"
- ">=wb_intercon-1.0"
- ">=wb_ram-1.0"
verilog_tb_files:
files:
- bench/verilog/orpsoc_tb.v
- bench/verilog/include/test-defines.v: {is_include_file: true}
file_type: verilogSource
depend:
- ">=elf-loader-1.0.3"
- ">=jtag_vpi-r2"
- ">=vlog_tb_utils-1.0"
verilator_tb_files:
files:
- bench/verilator/tb.cpp: {file_type: cppSource}
depend:
- verilator_tb_utils
targets:
mor1kx_tb: &sim
default_tool: icarus
filesets:
- soc_files
- mor1kx_modules
- "!tool_verilator ? (verilog_tb_files)"
- "tool_verilator ? (verilator_tb_files)"
parameters: [clear_ram, pipeline, feature_immu, feature_dmmu, feature_fpu,
feature_instructioncache, feature_datacache, feature_debugunit,
feature_cmov, feature_ext, option_rf_num_shadow_gpr]
tools:
icarus:
iverilog_options: [-DICARUS_SIM, -DSIM, -DSPEEDSIM]
modelsim:
vlog_options: [+define+SIM, +define+MODELSIM_SIM, -timescale 1ns/1ps]
vsim_options: [-L, altera_mf_ver, -L, altera_mf]
verilator:
verilator_options: [-Wno-fatal, --trace]
# Disable `cli_parser` option for now, 1 there is a bug in edalize that
# needs to get fixed otherwise this fails. Also, 2 we need a more
# features in command line parsing for this to work. For verilator we
# need the `pipeline` option to be send to the verilator builder, but
# the `elf-load` and `trace_enable` options should go to the simulator
# binary. Currently this only supports all options go to the build
# stage `managed` or all options go to the simulator `raw`.
# cli_parser: managed
toplevel:
- "!tool_verilator ? (orpsoc_tb)"
- "tool_verilator ? (orpsoc_top)"
marocchino_tb:
default_tool: icarus
filesets:
- soc_files
- marocchino_modules
- "!tool_verilator ? (verilog_tb_files)"
- "tool_verilator ? (verilator_tb_files)"
parameters: [clear_ram, pipeline=MAROCCHINO, feature_debugunit, feature_fpu,
option_rf_num_shadow_gpr]
tools:
icarus:
iverilog_options: [-DICARUS_SIM, -DSIM, -DSPEEDSIM]
modelsim:
vlog_options: [+define+SIM, +define+MODELSIM_SIM, -timescale 1ns/1ps]
vsim_options: [-L, altera_mf_ver, -L, altera_mf]
verilator:
verilator_options: [-Wno-fatal, --trace, "-CFLAGS -DMAROCCHINO",
-Gpipeline=\"MAROCCHINO\"]
# Disable cli_parser see comment above.
# cli_parser: managed
toplevel:
- "!tool_verilator ? (orpsoc_tb)"
- "tool_verilator ? (orpsoc_top)"
sim: *sim
parameters:
clear_ram:
datatype : bool
description: Preset RAM to a known value (0)
paramtype : plusarg
scope : private
pipeline:
datatype : str
description: Mor1kx pipeline to use CAPPUCCINO, ESPRESSO, PRONTOESPRESSO
paramtype : vlogparam
scope : private
feature_immu:
datatype : str
description: Instructure MMU selector, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_dmmu:
datatype : str
description: Data MMU selector, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_instructioncache:
datatype : str
description: Instructure cache selector, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_datacache:
datatype : str
description: Data cache selector, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_debugunit:
datatype : str
description: Enable debug unit, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_cmov:
datatype : str
description: Enable cmov instructions, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_ext:
datatype : str
description: Enable sign extension instructions, use ENABLED, NONE
paramtype : vlogparam
scope : private
feature_fpu:
datatype : str
description: Enable support for the 32-bit FPU, use ENABLED, NONE
paramtype : vlogparam
scope : private
option_rf_num_shadow_gpr:
datatype : int
description: Specify number of shadow gprs, use 0-32
paramtype : vlogparam
scope : private