From 54e8b8bc7fc0f12c080d515889a4a17d719c1cb9 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 11 Jan 2023 12:04:25 -0800 Subject: [PATCH 01/86] Add CRC documentation for PGP4 --- protocols/pgp/pgp4/core/rtl/Pgp4Pkg.vhd | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4Pkg.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4Pkg.vhd index b41260a5c2..8a2f9261ef 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4Pkg.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4Pkg.vhd @@ -74,6 +74,9 @@ package Pgp4Pkg is subtype PGP4_EOFC_BYTES_LAST_FIELD_C is natural range 15 downto 12; subtype PGP4_EOFC_CRC_FIELD_C is natural range 47 downto 16; + -- IEEE 802.3; CRC-32 + -- G(X) = x^32 +x^26 +x^23 +x^22 +x^16 +x^12 +x^11 +x^10 +x^8 +x^7 +x^5 +x^4 +x^2 +x +1 + -- https://users.ece.cmu.edu/~koopman/crc/c32/0x82608edb.txt constant PGP4_CRC_POLY_C : slv(31 downto 0) := X"04C11DB7"; function pgp4MakeLinkInfo ( @@ -223,6 +226,8 @@ package body Pgp4Pkg is kCodeWord : slv(63 downto 0)) return slv is + -- G(X) = x^8 + x^3 + x^2 + x^1 + 1 + -- https://users.ece.cmu.edu/~koopman/crc/c08/0x83.txt constant CRC_POLY_C : slv(7 downto 0) := X"07"; variable data : slv(55 downto 0); From cb1e43fe58aadaea7d1cf46e9b8d8f23f4b533af Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:39:31 -0700 Subject: [PATCH 02/86] Add additional debug to error report --- axi/axi-stream/rtl/AxiStreamResize.vhd | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/axi/axi-stream/rtl/AxiStreamResize.vhd b/axi/axi-stream/rtl/AxiStreamResize.vhd index 5e20a62652..16b9d1cf74 100644 --- a/axi/axi-stream/rtl/AxiStreamResize.vhd +++ b/axi/axi-stream/rtl/AxiStreamResize.vhd @@ -88,7 +88,10 @@ begin -- Make sure data widths are appropriate. assert ((SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) or (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0)) - report "Data widths must be even number multiples of each other" severity failure; + report "Data widths must be even number multiples of each other" & LF & + "SLV_BYTES_C= " & integer'image(SLV_BYTES_C) & LF & + "MST_BYTES_C= " & integer'image(MST_BYTES_C) + severity failure; -- When going from a large bus to a small bus, ready is necessary assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) From beb22a74b84a4615f587e600e0a4d3204c0e8a2b Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 27 Jul 2023 15:42:19 -0700 Subject: [PATCH 03/86] Update for latest rogue API --- python/surf/devices/microchip/_Axi24LC64FT.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index 5d66a39306..ccaabceecb 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -31,7 +31,7 @@ def __init__(self, self.add(pr.RemoteVariable( name = "Mem", description = "Memory Array", - size = (4*nelms), + offset = 0x0000, numValues = nelms, valueBits = 32, valueStride = 32, From cac2cbcf60dc22370c8da26f43c7b81666aaae4d Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 3 Aug 2023 14:19:14 -0700 Subject: [PATCH 04/86] Add feature to view all registers --- python/surf/xilinx/_AxiSysMonUltraScale.py | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index 0fda8f50ff..ca6fbea2a8 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -82,6 +82,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "WO", hidden = True, + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -92,6 +93,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "WO", hidden = True, + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -102,6 +104,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -122,6 +125,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, + groups = "NoConfig", )) ############################################### @@ -375,6 +379,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -385,6 +390,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, + groups = "NoConfig", )) self.addRemoteVariables( @@ -397,6 +403,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll number = 8, stride = 4, hidden = True, + groups = "NoConfig", ) # self.addRemoteVariables( @@ -436,6 +443,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitSize = 12, bitOffset = 0x4, mode = "RW", + groups = "NoConfig", )) self.add(pr.LinkVariable( @@ -455,6 +463,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitSize = 12, bitOffset = 0x4, mode = "RW", + groups = "NoConfig", )) self.add(pr.LinkVariable( @@ -475,6 +484,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, + groups = "NoConfig", )) self.addRemoteVariables( @@ -487,6 +497,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll number = 8, stride = 4, hidden = True, + groups = "NoConfig", ) self.addRemoteVariables( @@ -566,8 +577,9 @@ def convAuxVoltage(var): return round(var.dependencies[0].value() * 244e-6,3) def simpleView(self): - # Hide all the variable - self.hideVariables(hidden=True) - # Then unhide the most interesting ones - vars = self.simpleViewList - self.hideVariables(hidden=False, variables=vars) + if self.simpleViewList is not None: + # Hide all the variable + self.hideVariables(hidden=True) + # Then unhide the most interesting ones + vars = self.simpleViewList + self.hideVariables(hidden=False, variables=vars) From 017b7a4c05cd071e115541e46c3ce8aaf38318cd Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 3 Aug 2023 14:19:40 -0700 Subject: [PATCH 05/86] Remove some register variables from the config dump --- python/surf/axi/_AxiVersion.py | 3 +++ python/surf/devices/microchip/_Axi24LC64FT.py | 1 + 2 files changed, 4 insertions(+) diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index 33c3f32f43..eaa4716253 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -95,6 +95,7 @@ def parseUpTime(var,read): base = pr.UInt, mode = 'RW', hidden = True, + groups = 'NoConfig' )) self.add(pr.RemoteCommand( @@ -117,6 +118,7 @@ def parseUpTime(var,read): base = pr.UInt, mode = 'RW', hidden = True, + groups = 'NoConfig' )) @self.command(hidden=True) @@ -133,6 +135,7 @@ def FpgaReloadAtAddress(arg): bitOffset = 0x00, base = pr.UInt, mode = 'RW', + groups = 'NoConfig' )) @self.command(description = 'Toggle UserReset') diff --git a/python/surf/devices/microchip/_Axi24LC64FT.py b/python/surf/devices/microchip/_Axi24LC64FT.py index c9fc0b53b3..0239958593 100644 --- a/python/surf/devices/microchip/_Axi24LC64FT.py +++ b/python/surf/devices/microchip/_Axi24LC64FT.py @@ -36,5 +36,6 @@ def __init__(self, valueBits = 32, valueStride = 32, bitSize = 32 * nelms, + groups = 'NoConfig', # mode = "RO", )) From 99d6d5f6261fe4136682dc1cb9aa5744955a4c29 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Thu, 12 Oct 2023 13:33:20 -0700 Subject: [PATCH 06/86] Fix merge error --- xilinx/general/rtl/GtRxAlignCheck.vhd | 3 --- 1 file changed, 3 deletions(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index feed4e2193..533e2f673a 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -334,6 +334,3 @@ begin axilReadSlave => mAxilReadSlave); end rtl; - - -end rtl; From a88e0185cb5953e249e3f2a2fb7efa41d2a67cb4 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Wed, 17 Jan 2024 12:01:16 -0800 Subject: [PATCH 07/86] add RXRECCLKOUT functionality to the PGP2FC GT --- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 ++-- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 5 +++-- .../pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 9 ++++++--- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 6 ++++-- 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index d250500e57..b705a004c6 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:03e754925c96f2b62d86de34d37c9e23a3e0e94cf36d9de473fe9e0084e076c7 -size 313146 +oid sha256:44598e02aeab4733c5c014c81bf55c67b402f5340221ca793d1c43a8699c80c0 +size 313487 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index c0d60b9dbd..1d790d3728 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -155,7 +155,7 @@ "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_SOURCE": [ { "value": "X0Y4 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_SOURCE": [ { "value": "X0Y4 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], @@ -170,7 +170,7 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "29", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "28", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -922,6 +922,7 @@ "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index d923e25bcd..8c885043ee 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -5,11 +5,11 @@ ------------------------------------------------------------------------------- -- Description: PGPv2b GTY Ultrascale IP Core Wrapper ------------------------------------------------------------------------------- --- This file is part of 'Example Project Firmware'. +-- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the -- top-level directory of this distribution and at: -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'Example Project Firmware', including this file, +-- No part of 'SLAC Firmware Standard Library', including this file, -- may be copied, modified, propagated, or distributed except according to -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- @@ -57,6 +57,7 @@ entity Pgp2fcGtyCoreWrapper is rxDecErr : out slv(1 downto 0); rxPolarity : in sl; rxOutClk : out sl; + rxRecClk : out sl; -- raw recovered clock -- Tx Ports txReset : in sl; @@ -154,6 +155,7 @@ architecture mapping of Pgp2fcGtyCoreWrapper is rxctrl3_out : out std_logic_vector (7 downto 0); rxdlysresetdone_out : out std_logic_vector (0 downto 0); rxoutclk_out : out std_logic_vector (0 downto 0); + rxrecclkout_out : out std_logic_vector (0 downto 0); rxphaligndone_out : out std_logic_vector (0 downto 0); rxpmaresetdone_out : out std_logic_vector (0 downto 0); rxresetdone_out : out std_logic_vector (0 downto 0); @@ -322,6 +324,7 @@ begin rxdlysresetdone_out(0) => rxDlysResetDone, rxphaligndone_out(0) => rxPhyAlignDone, rxoutclk_out(0) => rxOutClkGt, + rxrecclkout_out(0) => rxRecClk, txoutclk_out(0) => txOutClkGt, -- unused rxpmaresetdone_out(0) => rxPmaResetDone, rxresetdone_out(0) => rxResetDone, @@ -419,7 +422,7 @@ begin drpAddr => drpAddr, -- [out] drpDi => drpDi, -- [out] drpDo => drpDo); -- [in] - + txctrl2 <= "000000" & txDataK; txUsrActive <= txUsrClkActive and txPmaResetDone; rxUsrActive <= rxUsrClkActive and rxPmaResetDone; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index ae960f4036..e79c1a662e 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -5,11 +5,11 @@ ------------------------------------------------------------------------------- -- Description: PGPv2b GTY Ultrascale Core Module ------------------------------------------------------------------------------- --- This file is part of 'Example Project Firmware'. +-- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the -- top-level directory of this distribution and at: -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'Example Project Firmware', including this file, +-- No part of 'SLAC Firmware Standard Library', including this file, -- may be copied, modified, propagated, or distributed except according to -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- @@ -52,6 +52,7 @@ entity Pgp2fcGtyUltra is gtRefClk : in sl; gtFabricRefClk : in sl; gtUserRefClk : in sl; + rxRecClk : out sl; -- Gt Serial IO pgpGtTxP : out sl; pgpGtTxN : out sl; @@ -212,6 +213,7 @@ begin rxDecErr => phyRxLaneIn.decErr, rxPolarity => RX_POLARITY_G, rxOutClk => pgpRxOutClk, + rxRecClk => rxRecClk, txReset => gtTxUserReset, txUsrClk => pgpTxClk, txUsrClkActive => pgpTxMmcmLocked, From 7bf95215ebe67b2a3a16bf04396edda3acf00d2d Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 4 Mar 2024 16:33:59 -0800 Subject: [PATCH 08/86] introduce Julian's bugfix --- xilinx/general/rtl/GtRxAlignCheck.vhd | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index 533e2f673a..cbe6d49bcc 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -118,12 +118,6 @@ architecture rtl of GtRxAlignCheck is signal rxClkFreq : slv(31 downto 0); signal refClkFreq : slv(31 downto 0); - -- attribute dont_touch : string; - -- attribute dont_touch of r : signal is "TRUE"; - -- attribute dont_touch of ack : signal is "TRUE"; - -- attribute dont_touch of txClkFreq : signal is "TRUE"; - -- attribute dont_touch of rxClkFreq : signal is "TRUE"; - begin U_refClkFreq : entity surf.SyncClockFreq @@ -179,6 +173,7 @@ begin -- Reset the flags v.rst := '0'; + v.locked := '0'; -- Reset the strobes v.rstRetryCnt := '0'; @@ -212,9 +207,8 @@ begin case r.state is ---------------------------------------------------------------------- when RESET_S => - -- Set the flags + -- Set the flag v.rst := '1'; - v.locked := '0'; -- Check the counter if (r.rstcnt = r.rstlen) then -- Wait for the reset transition @@ -230,8 +224,6 @@ begin end if; ---------------------------------------------------------------------- when READ_S => - -- Reset the flag - v.locked := '0'; -- Wait for the reset transition and check state of master AXI-Lite if (resetDone = '1') and (ack.done = '0') then -- Start the master AXI-Lite transaction @@ -267,7 +259,7 @@ begin end if; ---------------------------------------------------------------------- when LOCKED_S => - -- Set the flag (can now be reset only by an external resetIn/resetErr) + -- Set the flag v.locked := '1'; ---------------------------------------------------------------------- end case; @@ -278,7 +270,7 @@ begin end if; -- Check for user reset - if (resetIn = '1') or (resetErr = '1') then + if (resetIn = '1') or (resetErr = '1' and resetDone = '1') then -- Setup flags for reset state v.rst := '1'; v.req.request := '0'; From 6c78ccbd7a8ad567e73da97a6c2085327e89d622 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 5 Mar 2024 13:15:15 -0800 Subject: [PATCH 09/86] fix align checker lock register querying --- xilinx/general/rtl/GtRxAlignCheck.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index cbe6d49bcc..ea07181ada 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -193,10 +193,10 @@ begin axiSlaveRegister (axilEp, x"104", 0, v.last); axiSlaveRegisterR(axilEp, x"108", 0, txClkFreq); axiSlaveRegisterR(axilEp, x"10C", 0, rxClkFreq); - axiSlaveRegisterR(axilEp, x"110", 0, v.locked); + axiSlaveRegisterR(axilEp, x"110", 0, r.locked); axiSlaveRegister (axilEp, x"114", 0, v.override); axiSlaveRegister (axilEp, x"118", 0, v.rstRetryCnt); - axiSlaveRegisterR(axilEp, x"11C", 0, v.retryCnt); + axiSlaveRegisterR(axilEp, x"11C", 0, r.retryCnt); axiSlaveRegisterR(axilEp, x"120", 0, refClkFreq); From 8a2c5c2b0632fad1800ec41ac7d8f5ecd8c7f59f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 8 Mar 2024 20:07:33 -0800 Subject: [PATCH 10/86] Add txoutclk bufg_gt for now even though unused --- .../gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 8c885043ee..0c00d1e636 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -34,6 +34,8 @@ entity Pgp2fcGtyCoreWrapper is AXI_CLK_FREQ_G : real := 125.0e6; AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0')); port ( + -- Could use gtUserRefClk instead of stableClk + -- Then change stableRst to extRst stableClk : in sl; stableRst : in sl; @@ -332,7 +334,7 @@ begin txpmaresetdone_out(0) => txPmaResetDone, txresetdone_out(0) => txResetDone); - TIMING_RECCLK_BUFG_GT : BUFG_GT + RXOUTCLK_BUFG_GT : BUFG_GT port map ( I => rxOutClkGt, CE => '1', @@ -342,8 +344,19 @@ begin DIV => "000", O => rxOutClkB); + -- Cant seem to use txoutclk to drive txusrclk without placement errors -- if one does not use the userRefClk for the txOutClk, placement errors occur - txOutClkB <= gtUserRefClk; + TXOUTCLK_BUFG_GT : BUFG_GT + port map ( + I => txOutClkGt, + CE => '1', + CEMASK => '1', + CLR => '0', + CLRMASK => '1', + DIV => "000", + O => txOutClkB); + +-- txOutClkB <= gtUserRefClk; U_XBAR : entity surf.AxiLiteCrossbar generic map ( From 28f001b1ef9ebbd6317b72a5b64ebe05b47e0b97 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 8 Mar 2024 20:08:10 -0800 Subject: [PATCH 11/86] Add SEL_FABRIC_REFCLK_G generic --- .../gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 73 ++++++++++--------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index e79c1a662e..bc1be10756 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -30,24 +30,24 @@ use UNISIM.VCOMPONENTS.all; entity Pgp2fcGtyUltra is generic ( - TPD_G : time := 1 ns; - SIMULATION_G : boolean := false; - ---------------------------------------------------------------------------------------------- + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + -- GT Settings + SEL_FABRIC_REFCLK_G : boolean := false; -- PGP Settings - ---------------------------------------------------------------------------------------------- - FC_WORDS_G : integer range 1 to 8 := 1; - TX_POLARITY_G : sl := '0'; - RX_POLARITY_G : sl := '0'; - AXI_CLK_FREQ_G : real := 125.0e6; - AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); - TX_ENABLE_G : boolean := true; - RX_ENABLE_G : boolean := true; - PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter - VC_INTERLEAVE_G : integer := 0; -- Interleave Frames - NUM_VC_EN_G : integer range 1 to 4 := 4); + FC_WORDS_G : integer range 1 to 8 := 1; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + AXI_CLK_FREQ_G : real := 125.0e6; + AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + TX_ENABLE_G : boolean := true; + RX_ENABLE_G : boolean := true; + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + VC_INTERLEAVE_G : integer := 0; -- Interleave Frames + NUM_VC_EN_G : integer range 1 to 4 := 4); port ( -- GT Clocking - stableClk : in sl; -- GT needs a stable clock to "boot up" + stableClk : in sl; -- GT needs a stable clock to "boot up" stableRst : in sl; gtRefClk : in sl; gtFabricRefClk : in sl; @@ -61,13 +61,13 @@ entity Pgp2fcGtyUltra is -- Tx Clocking pgpTxReset : in sl; pgpTxResetDone : out sl; - pgpTxOutClk : out sl; -- recovered clock + pgpTxOutClk : out sl; -- recovered clock pgpTxClk : in sl; pgpTxMmcmLocked : in sl; -- Rx clocking pgpRxReset : in sl; pgpRxResetDone : out sl; - pgpRxOutClk : out sl; -- recovered clock + pgpRxOutClk : out sl; -- recovered clock pgpRxClk : in sl; pgpRxMmcmLocked : in sl; -- Non VC Rx Signals @@ -119,43 +119,43 @@ begin U_RstSync_1 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon port map ( - arst => pgpTxIn.resetGt, -- [in] - clk => stableClk, -- [in] - rstOut => resetGtSync); -- [out] + arst => pgpTxIn.resetGt, -- [in] + clk => stableClk, -- [in] + rstOut => resetGtSync); -- [out] gtHardReset <= resetGtSync or stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon port map ( - clk => stableClk, -- [in] - dataIn => phyRxInit, -- [in] - dataOut => phyRxInitSync); -- [out] + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => phyRxInitSync); -- [out] -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset U_RstSync_2 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon port map ( - arst => pgpRxIn.resetRx, -- [in] - clk => stableClk, -- [in] - rstOut => resetRxSync); -- [out] + arst => pgpRxIn.resetRx, -- [in] + clk => stableClk, -- [in] + rstOut => resetRxSync); -- [out] gtRxUserReset <= phyRxInitSync or resetRxSync; U_RstSync_3 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon port map ( - arst => pgpTxIn.resetTx, -- [in] - clk => stableClk, -- [in] - rstOut => gtTxUserReset); -- [out] + arst => pgpTxIn.resetTx, -- [in] + clk => stableClk, -- [in] + rstOut => gtTxUserReset); -- [out] U_Pgp2fcLane : entity surf.Pgp2fcLane generic map ( @@ -190,9 +190,10 @@ begin -------------------------- PgpGtyCoreWrapper_1 : entity surf.Pgp2fcGtyCoreWrapper generic map ( - TPD_G => TPD_G, - AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, - AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) + TPD_G => TPD_G, + SEL_FABRIC_REFCLK_G => SEL_FABRIC_REFCLK_G, + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) port map ( stableClk => stableClk, stableRst => gtHardReset, From c8195ce7374a31f729200bc5e1dd24e587588313 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 12 Mar 2024 10:50:48 -0700 Subject: [PATCH 12/86] crc rst fix (affects sim) --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd index 8f78be9319..ee24f6d646 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd @@ -321,7 +321,7 @@ begin end if; end process; - crcRst <= '1' when fcWordCount = FC_WORDS_G else '0'; + crcRst <= '1' when fcWordCount = FC_WORDS_G or pgpTxClkRst = '1' else '0'; crcEn <= '1' when curState = ST_FC_C else '0'; U_Crc7 : entity surf.CRC7Rtl From 55327932b8d40239f15d23c448a900b000751547 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 12 Mar 2024 10:53:57 -0700 Subject: [PATCH 13/86] justify; initialize signals --- protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd | 7 +++++-- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd b/protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd index cc623d3e35..fb61570ee1 100644 --- a/protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/CRC7Rtl.vhd @@ -26,9 +26,12 @@ entity CRC7Rtl is end CRC7Rtl; architecture imp_crc of CRC7Rtl is - signal lfsr_q: std_logic_vector (7 downto 0); - signal lfsr_c: std_logic_vector (7 downto 0); + + signal lfsr_q: std_logic_vector (7 downto 0) := (others => '0'); + signal lfsr_c: std_logic_vector (7 downto 0) := (others => '0'); + begin + crc_out <= lfsr_c when crc_en = '1' else lfsr_q; crc_out_r <= lfsr_q; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd index ee24f6d646..3983c7c333 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd @@ -322,7 +322,7 @@ begin end process; crcRst <= '1' when fcWordCount = FC_WORDS_G or pgpTxClkRst = '1' else '0'; - crcEn <= '1' when curState = ST_FC_C else '0'; + crcEn <= '1' when curState = ST_FC_C else '0'; U_Crc7 : entity surf.CRC7Rtl port map ( From 4e1a2acbb4edbf94613f5f47e52e0ea8aaf31675 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 12 Mar 2024 10:54:43 -0700 Subject: [PATCH 14/86] revert rst --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd index 3983c7c333..8b2fe22b4f 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd @@ -321,8 +321,8 @@ begin end if; end process; - crcRst <= '1' when fcWordCount = FC_WORDS_G or pgpTxClkRst = '1' else '0'; - crcEn <= '1' when curState = ST_FC_C else '0'; + crcRst <= '1' when fcWordCount = FC_WORDS_G else '0'; + crcEn <= '1' when curState = ST_FC_C else '0'; U_Crc7 : entity surf.CRC7Rtl port map ( From 2e2dc6cf6f47dae883674d39088ea000ef8f4e70 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 26 Mar 2024 09:17:47 -0700 Subject: [PATCH 15/86] Remove unused BUFG_GT for now --- .../rtl/Pgp2fcGtyCoreWrapper.vhd | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 0c00d1e636..a6eac5ed72 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -346,15 +346,15 @@ begin -- Cant seem to use txoutclk to drive txusrclk without placement errors -- if one does not use the userRefClk for the txOutClk, placement errors occur - TXOUTCLK_BUFG_GT : BUFG_GT - port map ( - I => txOutClkGt, - CE => '1', - CEMASK => '1', - CLR => '0', - CLRMASK => '1', - DIV => "000", - O => txOutClkB); +-- TXOUTCLK_BUFG_GT : BUFG_GT +-- port map ( +-- I => txOutClkGt, +-- CE => '1', +-- CEMASK => '1', +-- CLR => '0', +-- CLRMASK => '1', +-- DIV => "000", +-- O => txOutClkB); -- txOutClkB <= gtUserRefClk; From eebc2cdbc08764c824dd46cec9a720d3c9b3d38a Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 26 Mar 2024 09:18:49 -0700 Subject: [PATCH 16/86] Change buffBypassRxReset clock to rxUsrClk According to Vivado timing analysis, this is how that reset should be clocked --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index a6eac5ed72..9b2c227676 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -456,7 +456,7 @@ begin U_RstSyncRx : entity surf.RstSync generic map (TPD_G => TPD_G) - port map (clk => gtUserRefClk, + port map (clk => rxUsrClk, asyncRst => rstSyncRxIn, syncRst => buffBypassRxReset); From 513429e489f14d886452affff67856012f53d65d Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 26 Mar 2024 11:22:12 -0700 Subject: [PATCH 17/86] can now reset gt via upstream modules as well --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 9b2c227676..8d9461c0bc 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -442,8 +442,9 @@ begin cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); - rstSyncRxIn <= ite(USE_ALIGN_CHECK_G, rxResetAlignCheck, rxReset); - rxResetGt <= ite(USE_ALIGN_CHECK_G, rxResetAlignCheck, rxReset); + rstSyncRxIn <= rxResetAlignCheck or rxReset; + rxResetGt <= rxResetAlignCheck or rxReset; + txOutClk <= txOutClkB; rxOutClk <= rxOutClkB; From 5e6a9fd41320d2df2af7ffe9b56c33ab9b352d3d Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 26 Mar 2024 13:41:08 -0700 Subject: [PATCH 18/86] drive txoutclk with gtUserRefClk --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 8d9461c0bc..0085ac8c65 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -356,7 +356,7 @@ begin -- DIV => "000", -- O => txOutClkB); --- txOutClkB <= gtUserRefClk; + txOutClkB <= gtUserRefClk; U_XBAR : entity surf.AxiLiteCrossbar generic map ( From 3afa4632b657b2a9c3e8fe64b2dcba6e01e86058 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 26 Mar 2024 14:20:29 -0700 Subject: [PATCH 19/86] Add fc interface to passthrough --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd index b926d8164d..54ff311b39 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd @@ -40,11 +40,11 @@ entity Pgp2fcAxi is port ( -- TX PGP Interface (pgpTxClk domain) - pgpTxClk : in sl; - pgpTxClkRst : in sl; - pgpTxIn : out Pgp2fcTxInType; - pgpTxOut : in Pgp2fcTxOutType; - locTxIn : in Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; + pgpTxClk : in sl; + pgpTxClkRst : in sl; + pgpTxIn : out Pgp2fcTxInType; + pgpTxOut : in Pgp2fcTxOutType; + locTxIn : in Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; -- RX PGP Interface (pgpRxClk domain) pgpRxClk : in sl; @@ -518,6 +518,8 @@ begin pgpTxIn.flowCntlDis <= locTxIn.flowCntlDis or syncFlowCntlDis; pgpTxIn.resetTx <= locTxIn.resetTx or txReset; pgpTxIn.resetGt <= r.resetGt; + pgpTxIn.fcValid <= locTxIn.fcValid; + pgpTxIn.fcWord <= locTxIn.fcWord; ------------------------------------- From e106a5992f2e7d91b57448b6893b6a4e8fa03411 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 4 Jun 2024 14:13:43 -0700 Subject: [PATCH 20/86] Output PMA reset to be used to reset external MMCM Switch to XCI --- .../gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 11 +++++++---- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 5 ++++- protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl | 4 ++-- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 0085ac8c65..6cd9bcd6e5 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -52,6 +52,7 @@ entity Pgp2fcGtyCoreWrapper is rxReset : in sl; rxUsrClkActive : in sl; rxResetDone : out sl; + rxPmaResetDone : out sl; rxUsrClk : in sl; rxData : out slv(15 downto 0); rxDataK : out slv(1 downto 0); @@ -210,7 +211,7 @@ architecture mapping of Pgp2fcGtyCoreWrapper is signal rxPmaReset : sl := '0'; signal txPcsReset : sl := '0'; signal txPmaReset : sl := '0'; - signal rxPmaResetDone : sl := '0'; + signal rxPmaResetDoneInt : sl := '0'; signal txPmaResetDone : sl := '0'; signal rxByteIsAligned : sl := '0'; signal rxByteReAlign : sl := '0'; @@ -255,7 +256,7 @@ begin gtwiz_userclk_tx_active_in(0) => txUsrActive, gtwiz_userclk_rx_active_in(0) => rxUsrActive, gtwiz_reset_clk_freerun_in(0) => stableClk, - gtwiz_reset_all_in(0) => stableRst, + gtwiz_reset_all_in(0) => '0', gtwiz_buffbypass_tx_reset_in(0) => buffBypassTxReset, gtwiz_buffbypass_tx_start_user_in(0) => buffBypassTxStart, gtwiz_buffbypass_tx_done_out(0) => buffBypassTxDone, @@ -328,7 +329,7 @@ begin rxoutclk_out(0) => rxOutClkGt, rxrecclkout_out(0) => rxRecClk, txoutclk_out(0) => txOutClkGt, -- unused - rxpmaresetdone_out(0) => rxPmaResetDone, + rxpmaresetdone_out(0) => rxPmaResetDoneInt, rxresetdone_out(0) => rxResetDone, rxsyncdone_out(0) => rxSyncDone, txpmaresetdone_out(0) => txPmaResetDone, @@ -438,7 +439,9 @@ begin txctrl2 <= "000000" & txDataK; txUsrActive <= txUsrClkActive and txPmaResetDone; - rxUsrActive <= rxUsrClkActive and rxPmaResetDone; + rxUsrActive <= rxUsrClkActive and rxPmaResetDoneInt; + + rxPmaResetDone <= rxPmaResetDoneInt; cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index bc1be10756..1f26285974 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -67,6 +67,7 @@ entity Pgp2fcGtyUltra is -- Rx clocking pgpRxReset : in sl; pgpRxResetDone : out sl; + pgpRxPmaResetDone : out sl; pgpRxOutClk : out sl; -- recovered clock pgpRxClk : in sl; pgpRxMmcmLocked : in sl; @@ -105,7 +106,7 @@ architecture mapping of Pgp2fcGtyUltra is signal phyRxInit : sl; -- PgpTx Signals - signal gtTxUserReset : sl; + signal gtTxUserReset : sl := '0'; signal phyTxLaneOut : Pgp2fcTxPhyLaneOutType; signal phyTxReady : sl; @@ -126,6 +127,7 @@ begin rstOut => resetGtSync); -- [out] gtHardReset <= resetGtSync or stableRst; + gtHardReset <= stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( @@ -207,6 +209,7 @@ begin rxReset => gtRxUserReset, rxUsrClkActive => pgpRxMmcmLocked, rxResetDone => phyRxReady, + rxPmaResetDone => pgpRxPmaResetDone, rxUsrClk => pgpRxClk, rxData => phyRxLaneIn.data, rxDataK => phyRxLaneIn.dataK, diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl index 565e8facf8..a715153cbe 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl @@ -6,8 +6,8 @@ if { $::env(VIVADO_VERSION) >= 2020.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" - loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" - #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" + #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" + loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" From 094e12c3c93aaa21f9bdb802a9752684667e896c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 4 Jun 2024 16:24:51 -0700 Subject: [PATCH 21/86] Switch back to DCP --- protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl index a715153cbe..565e8facf8 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl @@ -6,8 +6,8 @@ if { $::env(VIVADO_VERSION) >= 2020.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" - #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" - loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" + loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" + #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" From 69d5442b8d748b61ba65b64d38fe1e525e616aac Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 4 Jun 2024 16:44:51 -0700 Subject: [PATCH 22/86] Remove old line --- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 1f26285974..8b4b6d7f5a 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -126,7 +126,7 @@ begin clk => stableClk, -- [in] rstOut => resetGtSync); -- [out] - gtHardReset <= resetGtSync or stableRst; + --gtHardReset <= resetGtSync or stableRst; gtHardReset <= stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot From 5d0f6fe199d90178fe0255e145b4c9610af0a684 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 10 Jun 2024 22:21:01 -0700 Subject: [PATCH 23/86] Add default value to avoid simulation errors --- .../AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd index 4a86948b48..c395726976 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -137,7 +137,7 @@ architecture rtl of Ad9249ReadoutGroup2 is signal debugDataValid : sl; signal debugDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); - signal debugDataTmp : slv16Array(7 downto 0); + signal debugDataTmp : slv16Array(7 downto 0) := (others => (others => '0')); signal invertSync : sl; signal bitSlip : sl; From fda1f5a82277b4080f8b7c34090789be8eee74ba Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 10 Jun 2024 22:21:22 -0700 Subject: [PATCH 24/86] Fix incomplete sensitivity list --- devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd index 02db1c9676..c32dc61e45 100644 --- a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd @@ -532,7 +532,7 @@ begin end if; end process seq; - adcComb : process (adcR) is + adcComb : process (adcR, r, vin) is variable v : AdcRegType := ADC_REG_INIT_C; begin v := adcR; From d03eef711426ee64a540b3272966b0d52721d163 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 10 Jun 2024 22:22:57 -0700 Subject: [PATCH 25/86] Resolve 'X' and 'U' on DRPDO output from MMCM to zeros to avoid simulation issues --- .../clocking/rtl/ClockManagerUltraScale.vhd | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd b/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd index a775879473..17c8a3e7d0 100644 --- a/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd +++ b/xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd @@ -107,8 +107,8 @@ architecture rtl of ClockManagerUltraScale is signal rstInLoc : sl; signal clkInLoc : sl; signal lockedLoc : sl; - signal clkOutMmcm : slv(6 downto 0); - signal clkOutLoc : slv(6 downto 0); + signal clkOutMmcm : slv(6 downto 0) := (others => '0'); + signal clkOutLoc : slv(6 downto 0) := (others => '0'); signal clkFbOut : sl; signal clkFbIn : sl; @@ -117,7 +117,8 @@ architecture rtl of ClockManagerUltraScale is signal drpWe : sl; signal drpAddr : slv(6 downto 0); signal drpDi : slv(15 downto 0); - signal drpDo : slv(15 downto 0); + signal drpDo : slv(15 downto 0) := (others => '0'); + signal drpDo01 : slv(15 downto 0) := (others => '0'); attribute keep_hierarchy : string; attribute keep_hierarchy of rtl : architecture is "yes"; @@ -156,7 +157,9 @@ begin drpWe => drpWe, drpAddr => drpAddr, drpDi => drpDi, - drpDo => drpDo); + drpDo => drpDo01); + + drpDo01 <= to_stdLogicVector(to_bitvector(drpDo)); MmcmGen : if (TYPE_G = "MMCM") and (SIMULATION_G = false) generate U_Mmcm : MMCME4_ADV From 387ed34c22e42361e6940c90616345183936bfa6 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 11 Jun 2024 10:00:49 -0700 Subject: [PATCH 26/86] removing 'project_parameters' from .XCI so it can be used across multiple types of FPGA fabric --- .../pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index 1d790d3728..d7b7ede705 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -821,21 +821,6 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "virtexuplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xcvu9p" } ], - "PACKAGE": [ { "value": "fsgd2104" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], - "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], - "USE_RDI_GENERATION": [ { "value": "TRUE" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], From 41228e21a567556b1fe39c97591720d6e4cce4c9 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 12:09:09 -0700 Subject: [PATCH 27/86] Fix whitespace --- python/surf/xilinx/_AxiSysMonUltraScale.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index e431da7397..e9afbd9c00 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -96,7 +96,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "WO", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -107,7 +107,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -128,7 +128,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) ############################################### @@ -383,7 +383,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) self.add(pr.RemoteVariable( @@ -394,7 +394,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) self.addRemoteVariables( @@ -407,7 +407,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll number = 8, stride = 4, hidden = True, - groups = "NoConfig", + groups = "NoConfig", ) # self.addRemoteVariables( @@ -447,7 +447,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitSize = 12, bitOffset = 0x4, mode = "RW", - groups = "NoConfig", + groups = "NoConfig", )) self.add(pr.LinkVariable( @@ -467,7 +467,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitSize = 12, bitOffset = 0x4, mode = "RW", - groups = "NoConfig", + groups = "NoConfig", )) self.add(pr.LinkVariable( @@ -488,7 +488,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll bitOffset = 0x00, mode = "RW", hidden = True, - groups = "NoConfig", + groups = "NoConfig", )) self.addRemoteVariables( @@ -501,7 +501,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll number = 8, stride = 4, hidden = True, - groups = "NoConfig", + groups = "NoConfig", ) self.addRemoteVariables( From 46e0615979209003da209b42bf9c07a4e3d486f4 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 12:11:54 -0700 Subject: [PATCH 28/86] Fix whitespace --- python/surf/axi/_AxiVersion.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index eaa4716253..b9e668cc33 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -118,7 +118,7 @@ def parseUpTime(var,read): base = pr.UInt, mode = 'RW', hidden = True, - groups = 'NoConfig' + groups = 'NoConfig' )) @self.command(hidden=True) @@ -135,7 +135,7 @@ def FpgaReloadAtAddress(arg): bitOffset = 0x00, base = pr.UInt, mode = 'RW', - groups = 'NoConfig' + groups = 'NoConfig' )) @self.command(description = 'Toggle UserReset') From c10de0d769a2b02ff5990893185737e300093b7e Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 12:32:09 -0700 Subject: [PATCH 29/86] Fix whitespace --- python/surf/axi/_AxiVersion.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index b9e668cc33..5b486a89fd 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -118,7 +118,7 @@ def parseUpTime(var,read): base = pr.UInt, mode = 'RW', hidden = True, - groups = 'NoConfig' + groups = 'NoConfig', )) @self.command(hidden=True) @@ -135,7 +135,7 @@ def FpgaReloadAtAddress(arg): bitOffset = 0x00, base = pr.UInt, mode = 'RW', - groups = 'NoConfig' + groups = 'NoConfig', )) @self.command(description = 'Toggle UserReset') From 1e4531e5cf3ff0f386b00e3630d7d47987651cdb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 13:45:17 -0700 Subject: [PATCH 30/86] Add gth IP core for PGPFC --- .../gthUltraScale+/ip/Pgp2fcGthCore.dcp | 3 + .../gthUltraScale+/ip/Pgp2fcGthCore.xci | 929 ++++++++++++++++++ .../rtl/Pgp2fcGthCoreWrapper.vhd | 467 +++++++++ .../gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 237 +++++ .../pgp/pgp2fc/gthUltraScale+/ruckus.tcl | 14 + 5 files changed, 1650 insertions(+) create mode 100644 protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp create mode 100644 protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci create mode 100644 protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd create mode 100644 protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd create mode 100644 protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp new file mode 100644 index 0000000000..94986d2380 --- /dev/null +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:22e243c27bc43679a281ba0094d67ec10d60a8ecc38d454d6dcbe3ba5d445ea0 +size 313652 diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci new file mode 100644 index 0000000000..7204351628 --- /dev/null +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -0,0 +1,929 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Pgp2fcGthCore", + "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", + "ip_revision": "16", + "gen_directory": "../../../../zCCM_kria_project.gen/sources_1/ip/Pgp2fcGthCore", + "parameters": { + "component_parameters": { + "GT_TYPE": [ { "value": "GTH", "resolve_type": "user", "usage": "all" } ], + "INTERNAL_GT_PRIM_TYPE": [ { "value": "gthe4", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "GT_REV": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ], + "RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], + "TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], + "CHANNEL_ENABLE": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_MASTER_CHANNEL": [ { "value": "X0Y4", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_MASTER_CHANNEL": [ { "value": "X0Y4", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "LOCATE_COMMON": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "INTERNAL_NUM_COMMONS_CORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ], + "OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INS_LOSS_NYQ": [ { "value": "14", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_PLL_TYPE": [ { "value": "CPLL", "resolve_type": "user", "usage": "all" } ], + "TX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_DATA_ENCODING": [ { "value": "8B10B", "resolve_type": "user", "usage": "all" } ], + "TX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_OUTCLK_SOURCE": [ { "value": "TXPLLREFCLK_DIV1", "resolve_type": "user", "usage": "all" } ], + "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ], + "RX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_PLL_TYPE": [ { "value": "CPLL", "resolve_type": "user", "usage": "all" } ], + "RX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_DATA_DECODING": [ { "value": "8B10B", "resolve_type": "user", "usage": "all" } ], + "RX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], + "RX_JTOL_FC": [ { "value": "2.2281258", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_OUTCLK_SOURCE": [ { "value": "RXOUTCLKPMA", "resolve_type": "user", "usage": "all" } ], + "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ], + 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"0x0" } ], + "rxusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "tx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], + "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], + "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], + "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllfbclklost_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cplllock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllrefclklost_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdo_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drprdy_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gthtxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gthtxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyteisaligned_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyterealign_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcommadet_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxctrl0_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl1_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl2_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxctrl3_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxdlysresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd new file mode 100644 index 0000000000..aeb636b3ca --- /dev/null +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -0,0 +1,467 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PGPv2b GTH Ultrascale IP Core Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp2fcGthCoreWrapper is + generic ( + TPD_G : time := 1 ns; + SEL_FABRIC_REFCLK_G : boolean := false; + USE_ALIGN_CHECK_G : boolean := true; + AXI_CLK_FREQ_G : real := 125.0e6; + AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0')); + port ( + -- Could use gtUserRefClk instead of stableClk + -- Then change stableRst to extRst + stableClk : in sl; + stableRst : in sl; + + -- GTH FPGA IO + gtRefClk : in sl; + gtFabricRefClk : in sl; + gtUserRefClk : in sl; + gtRxP : in sl; + gtRxN : in sl; + gtTxP : out sl; + gtTxN : out sl; + + -- Rx ports + rxReset : in sl; + rxUsrClkActive : in sl; + rxResetDone : out sl; + rxPmaResetDone : out sl; + rxUsrClk : in sl; + rxData : out slv(15 downto 0); + rxDataK : out slv(1 downto 0); + rxDispErr : out slv(1 downto 0); + rxDecErr : out slv(1 downto 0); + rxPolarity : in sl; + rxOutClk : out sl; + rxRecClk : out sl; -- raw recovered clock + + -- Tx Ports + txReset : in sl; + txUsrClk : in sl; + txUsrClkActive : in sl; + txResetDone : out sl; + txData : in slv(15 downto 0); + txDataK : in slv(1 downto 0); + txPolarity : in sl; + txOutClk : out sl; + loopback : in slv(2 downto 0); + + -- AXI-Lite DRP interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); + +end entity Pgp2fcGthCoreWrapper; + +architecture mapping of Pgp2fcGthCoreWrapper is + + component Pgp2fcGthCore + port ( + gtwiz_userclk_tx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_userclk_tx_active_in : in std_logic_vector (0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_start_user_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_done_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_error_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_start_user_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_done_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_error_out : out std_logic_vector (0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector (0 downto 0); + gtwiz_reset_all_in : in std_logic_vector (0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector (0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector (0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector (0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector (15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector (15 downto 0); + cpllrefclksel_in : in std_logic_vector (2 downto 0); + cplllockdetclk_in : in std_logic_vector (0 downto 0); + cplllocken_in : in std_logic_vector (0 downto 0); + drpaddr_in : in std_logic_vector (9 downto 0); + drpclk_in : in std_logic_vector (0 downto 0); + drpdi_in : in std_logic_vector (15 downto 0); + drpen_in : in std_logic_vector (0 downto 0); + drpwe_in : in std_logic_vector (0 downto 0); + gtgrefclk_in : in std_logic_vector (0 downto 0); + gtrefclk0_in : in std_logic_vector (0 downto 0); + gthrxn_in : in std_logic_vector (0 downto 0); + gthrxp_in : in std_logic_vector (0 downto 0); + loopback_in : in std_logic_vector (2 downto 0); + rx8b10ben_in : in std_logic_vector (0 downto 0); + rxcdrreset_in : in std_logic_vector (0 downto 0); + rxcommadeten_in : in std_logic_vector (0 downto 0); + rxmcommaalignen_in : in std_logic_vector (0 downto 0); + rxpcommaalignen_in : in std_logic_vector (0 downto 0); + rxpcsreset_in : in std_logic_vector (0 downto 0); + rxpmareset_in : in std_logic_vector (0 downto 0); + rxpolarity_in : in std_logic_vector (0 downto 0); + rxusrclk_in : in std_logic_vector (0 downto 0); + rxusrclk2_in : in std_logic_vector (0 downto 0); + tx8b10ben_in : in std_logic_vector (0 downto 0); + txctrl0_in : in std_logic_vector (15 downto 0); + txctrl1_in : in std_logic_vector (15 downto 0); + txctrl2_in : in std_logic_vector (7 downto 0); + txpcsreset_in : in std_logic_vector (0 downto 0); + txpmareset_in : in std_logic_vector (0 downto 0); + txpolarity_in : in std_logic_vector (0 downto 0); + txusrclk_in : in std_logic_vector (0 downto 0); + txusrclk2_in : in std_logic_vector (0 downto 0); + cpllfbclklost_out : out std_logic_vector (0 downto 0); + cplllock_out : out std_logic_vector (0 downto 0); + cpllrefclklost_out : out std_logic_vector (0 downto 0); + drpdo_out : out std_logic_vector (15 downto 0); + drprdy_out : out std_logic_vector (0 downto 0); + gtpowergood_out : out std_logic_vector (0 downto 0); + gthtxn_out : out std_logic_vector (0 downto 0); + gthtxp_out : out std_logic_vector (0 downto 0); + rxbyteisaligned_out : out std_logic_vector (0 downto 0); + rxbyterealign_out : out std_logic_vector (0 downto 0); + rxcommadet_out : out std_logic_vector (0 downto 0); + rxctrl0_out : out std_logic_vector (15 downto 0); + rxctrl1_out : out std_logic_vector (15 downto 0); + rxctrl2_out : out std_logic_vector (7 downto 0); + rxctrl3_out : out std_logic_vector (7 downto 0); + rxdlysresetdone_out : out std_logic_vector (0 downto 0); + rxoutclk_out : out std_logic_vector (0 downto 0); + rxrecclkout_out : out std_logic_vector (0 downto 0); + rxphaligndone_out : out std_logic_vector (0 downto 0); + rxpmaresetdone_out : out std_logic_vector (0 downto 0); + rxresetdone_out : out std_logic_vector (0 downto 0); + rxsyncdone_out : out std_logic_vector (0 downto 0); + txoutclk_out : out std_logic_vector (0 downto 0); + txpmaresetdone_out : out std_logic_vector (0 downto 0); + txresetdone_out : out std_logic_vector (0 downto 0)); + end component; + + constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(1 downto 0) := ( + 0 => ( + baseAddr => (AXI_BASE_ADDR_G), + addrBits => 12, + connectivity => x"FFFF"), + 1 => ( + baseAddr => (AXI_BASE_ADDR_G+x"1000"), + addrBits => 12, + connectivity => x"FFFF")); + + signal axilWriteMasters : AxiLiteWriteMasterArray(1 downto 0); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(1 downto 0); + signal axilReadMasters : AxiLiteReadMasterArray(1 downto 0); + signal axilReadSlaves : AxiLiteReadSlaveArray(1 downto 0); + + signal mAxilWriteMaster : AxiLiteWriteMasterType; + signal mAxilWriteSlave : AxiLiteWriteSlaveType; + signal mAxilReadMaster : AxiLiteReadMasterType; + signal mAxilReadSlave : AxiLiteReadSlaveType; + + signal drpAddr : slv(9 downto 0) := (others => '0'); + signal drpDi : slv(15 downto 0) := (others => '0'); + signal drpDo : slv(15 downto 0) := (others => '0'); + signal drpEn : sl := '0'; + signal drpWe : sl := '0'; + signal drpRdy : sl := '0'; + signal dummy0_6 : slv(5 downto 0) := (others => '0'); + signal dummy1_14 : slv(13 downto 0) := (others => '0'); + signal dummy2_14 : slv(13 downto 0) := (others => '0'); + signal dummy3_6 : slv(5 downto 0) := (others => '0'); + signal dummy4_1 : sl := '0'; + signal dummy5_1 : sl := '0'; + signal txctrl2 : slv(7 downto 0) := (others => '0'); + + signal cPllRefClkSel : slv(2 downto 0) := (others => '0'); + signal cPllFbClkLost : sl := '0'; + signal cPllLock : sl := '0'; + signal cPllRefClkLost : sl := '0'; + signal rxCdrReset : sl := '0'; + signal rxPcsReset : sl := '0'; + signal rxPmaReset : sl := '0'; + signal txPcsReset : sl := '0'; + signal txPmaReset : sl := '0'; + signal rxPmaResetDoneInt : sl := '0'; + signal txPmaResetDone : sl := '0'; + signal rxByteIsAligned : sl := '0'; + signal rxByteReAlign : sl := '0'; + signal rxCommaDet : sl := '0'; + signal txUsrActive : sl := '0'; + signal rxUsrActive : sl := '0'; + signal rxMcommaAlignEn : sl := '1'; + signal rxPcommaAlignEn : sl := '1'; + signal buffBypassTxReset : sl := '0'; + signal buffBypassTxStart : sl := '0'; + signal buffBypassTxDone : sl := '0'; + signal buffBypassTxError : sl := '0'; + signal buffBypassRxReset : sl := '0'; + signal buffBypassRxStart : sl := '0'; + signal buffBypassRxDone : sl := '0'; + signal buffBypassRxError : sl := '0'; + signal rxDlysResetDone : sl := '0'; + signal rxPhyAlignDone : sl := '0'; + signal rxSyncDone : sl := '0'; + signal txResetGt : sl := '0'; + signal rxResetGt : sl := '0'; + signal rxResetAlignCheck : sl := '0'; + signal rstSyncRxIn : sl := '0'; + signal rxStatusLocked : sl := '0'; + signal rxOutClkGt : sl := '0'; + signal txOutClkGt : sl := '0'; + signal rxOutClkB : sl := '0'; + signal txOutClkB : sl := '0'; + +begin + + -- Has to be generated from aurora core in order to work properly. + -- Also, look out for the K-character 8b/10b alignment parameters; + -- sometimes the core resets these to the default value (K28.5). + -- The 8b/10b decoder aligns automatically for K28.1 (PGP2FC). + -- The core features a GTGrefclk port, that should be connected + -- to a fabric-generated clock (idea stolen from LCLS-II timing repo). + -- This will only work if the fabric clock is 185.714MHz, and if + -- the associated generic is set to true. + U_Pgp2fcGthCore : Pgp2fcGthCore + port map ( + gtwiz_userclk_tx_active_in(0) => txUsrActive, + gtwiz_userclk_rx_active_in(0) => rxUsrActive, + gtwiz_reset_clk_freerun_in(0) => stableClk, + gtwiz_reset_all_in(0) => '0', + gtwiz_buffbypass_tx_reset_in(0) => buffBypassTxReset, + gtwiz_buffbypass_tx_start_user_in(0) => buffBypassTxStart, + gtwiz_buffbypass_tx_done_out(0) => buffBypassTxDone, + gtwiz_buffbypass_tx_error_out(0) => buffBypassTxError, + gtwiz_buffbypass_rx_reset_in(0) => buffBypassRxReset, + gtwiz_buffbypass_rx_start_user_in(0) => buffBypassRxStart, + gtwiz_buffbypass_rx_done_out(0) => buffBypassRxDone, + gtwiz_buffbypass_rx_error_out(0) => buffBypassRxError, + gtwiz_userclk_tx_reset_in(0) => buffBypassTxReset, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => txReset, + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => rxResetGt, + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out => open, + gtwiz_reset_rx_done_out => open, + gtwiz_userdata_tx_in => txData, + gtwiz_userdata_rx_out => rxData, + cpllrefclksel_in => cPllRefClkSel, + cplllockdetclk_in(0) => stableClk, + cplllocken_in(0) => '1', + cpllfbclklost_out(0) => cPllFbClkLost, + cplllock_out(0) => cPllLock, + cpllrefclklost_out(0) => cPllRefClkLost, + drpclk_in(0) => stableClk, + drpaddr_in => drpAddr, + drpdi_in => drpDi, + drpen_in(0) => drpEn, + drpwe_in(0) => drpWe, + drpdo_out => drpDo, + drprdy_out(0) => drpRdy, + gthrxn_in(0) => gtRxN, + gthrxp_in(0) => gtRxP, + gtgrefclk_in(0) => gtFabricRefClk, + gtrefclk0_in(0) => gtRefClk, + loopback_in => loopback, + rx8b10ben_in(0) => '1', + rxcdrreset_in(0) => rxCdrReset, + rxcommadeten_in(0) => '1', + rxmcommaalignen_in(0) => rxMcommaAlignEn, + rxpcommaalignen_in(0) => rxPcommaAlignEn, + rxpcsreset_in(0) => rxPcsReset, + rxpmareset_in(0) => rxPmaReset, + txpcsreset_in(0) => txPcsReset, + txpmareset_in(0) => txPmaReset, + rxpolarity_in(0) => rxPolarity, + rxusrclk_in(0) => rxUsrClk, + rxusrclk2_in(0) => rxUsrClk, + tx8b10ben_in(0) => '1', + txctrl0_in => X"0000", + txctrl1_in => X"0000", + txctrl2_in => txctrl2, + txpolarity_in(0) => txPolarity, + txusrclk_in(0) => txUsrClk, + txusrclk2_in(0) => txUsrClk, + gthtxn_out(0) => gtTxN, + gthtxp_out(0) => gtTxP, + rxbyteisaligned_out(0) => rxByteIsAligned, + rxbyterealign_out(0) => rxByteReAlign, + rxcommadet_out(0) => rxCommaDet, + rxctrl0_out(1 downto 0) => rxDataK, + rxctrl0_out(15 downto 2) => dummy1_14, + rxctrl1_out(1 downto 0) => rxDispErr, + rxctrl1_out(15 downto 2) => dummy2_14, + rxctrl2_out => open, + rxctrl3_out(1 downto 0) => rxDecErr, + rxctrl3_out(7 downto 2) => dummy0_6, + rxdlysresetdone_out(0) => rxDlysResetDone, + rxphaligndone_out(0) => rxPhyAlignDone, + rxoutclk_out(0) => rxOutClkGt, + rxrecclkout_out(0) => rxRecClk, + txoutclk_out(0) => txOutClkGt, -- unused + rxpmaresetdone_out(0) => rxPmaResetDoneInt, + rxresetdone_out(0) => rxResetDone, + rxsyncdone_out(0) => rxSyncDone, + txpmaresetdone_out(0) => txPmaResetDone, + txresetdone_out(0) => txResetDone); + + RXOUTCLK_BUFG_GT : BUFG_GT + port map ( + I => rxOutClkGt, + CE => '1', + CEMASK => '1', + CLR => '0', + CLRMASK => '1', + DIV => "000", + O => rxOutClkB); + + -- Cant seem to use txoutclk to drive txusrclk without placement errors + -- if one does not use the userRefClk for the txOutClk, placement errors occur +-- TXOUTCLK_BUFG_GT : BUFG_GT +-- port map ( +-- I => txOutClkGt, +-- CE => '1', +-- CEMASK => '1', +-- CLR => '0', +-- CLRMASK => '1', +-- DIV => "000", +-- O => txOutClkB); + + txOutClkB <= gtUserRefClk; + + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 2, + NUM_MASTER_SLOTS_G => 2, + MASTERS_CONFIG_G => AXI_CROSSBAR_MASTERS_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteMasters(1) => mAxilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiWriteSlaves(1) => mAxilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadMasters(1) => mAxilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + sAxiReadSlaves(1) => mAxilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + U_AlignCheck : entity surf.GtRxAlignCheck + generic map ( + TPD_G => TPD_G, + GT_TYPE_G => "GTHE4", + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) + port map ( + -- Clock Monitoring + txClk => txUsrClk, + rxClk => rxUsrClk, + refClk => gtUserRefClk, + -- GTH Status/Control Interface + resetIn => rxReset, + resetDone => buffBypassRxDone, + resetErr => buffBypassRxError, + resetOut => rxResetAlignCheck, + locked => rxStatusLocked, + -- Clock and Reset + axilClk => axilClk, + axilRst => axilRst, + -- Slave AXI-Lite Interface + mAxilReadMaster => mAxilReadMaster, + mAxilReadSlave => mAxilReadSlave, + mAxilWriteMaster => mAxilWriteMaster, + mAxilWriteSlave => mAxilWriteSlave, + -- Slave AXI-Lite Interface + sAxilReadMaster => axilReadMasters(0), + sAxilReadSlave => axilReadSlaves(0), + sAxilWriteMaster => axilWriteMasters(0), + sAxilWriteSlave => axilWriteSlaves(0)); + + U_AxiLiteToDrp_1 : entity surf.AxiLiteToDrp + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => false, + EN_ARBITRATION_G => false, + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 16) + port map ( + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => axilReadMasters(1), -- [in] + axilReadSlave => axilReadSlaves(1), -- [out] + axilWriteMaster => axilWriteMasters(1), -- [in] + axilWriteSlave => axilWriteSlaves(1), -- [out] + drpClk => stableClk, -- [in] + drpRst => stableRst, -- [in] + drpReq => open, -- [out] + drpRdy => drpRdy, -- [in] + drpEn => drpEn, -- [out] + drpWe => drpWe, -- [out] + drpUsrRst => open, -- [out] + drpAddr => drpAddr, -- [out] + drpDi => drpDi, -- [out] + drpDo => drpDo); -- [in] + + txctrl2 <= "000000" & txDataK; + txUsrActive <= txUsrClkActive and txPmaResetDone; + rxUsrActive <= rxUsrClkActive and rxPmaResetDoneInt; + + rxPmaResetDone <= rxPmaResetDoneInt; + + cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); + + rstSyncRxIn <= rxResetAlignCheck or rxReset; + rxResetGt <= rxResetAlignCheck or rxReset; + + + txOutClk <= txOutClkB; + rxOutClk <= rxOutClkB; + + U_RstSyncTx : entity surf.RstSync + generic map (TPD_G => TPD_G) + port map (clk => gtUserRefClk, + asyncRst => txReset, + syncRst => buffBypassTxReset); + + U_RstSyncRx : entity surf.RstSync + generic map (TPD_G => TPD_G) + port map (clk => rxUsrClk, + asyncRst => rstSyncRxIn, + syncRst => buffBypassRxReset); + +end architecture mapping; diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd new file mode 100644 index 0000000000..125062768b --- /dev/null +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -0,0 +1,237 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PGPv2b GTH Ultrascale Core Module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.Pgp2fcPkg.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity Pgp2fcGthUltra is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + -- GT Settings + SEL_FABRIC_REFCLK_G : boolean := false; + -- PGP Settings + FC_WORDS_G : integer range 1 to 8 := 1; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + AXI_CLK_FREQ_G : real := 125.0e6; + AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + TX_ENABLE_G : boolean := true; + RX_ENABLE_G : boolean := true; + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + VC_INTERLEAVE_G : integer := 0; -- Interleave Frames + NUM_VC_EN_G : integer range 1 to 4 := 4); + port ( + -- GT Clocking + stableClk : in sl; -- GT needs a stable clock to "boot up" + stableRst : in sl; + gtRefClk : in sl; + gtFabricRefClk : in sl; + gtUserRefClk : in sl; + rxRecClk : out sl; + -- Gt Serial IO + pgpGtTxP : out sl; + pgpGtTxN : out sl; + pgpGtRxP : in sl; + pgpGtRxN : in sl; + -- Tx Clocking + pgpTxReset : in sl; + pgpTxResetDone : out sl; + pgpTxOutClk : out sl; -- recovered clock + pgpTxClk : in sl; + pgpTxMmcmLocked : in sl; + -- Rx clocking + pgpRxReset : in sl; + pgpRxResetDone : out sl; + pgpRxPmaResetDone : out sl; + pgpRxOutClk : out sl; -- recovered clock + pgpRxClk : in sl; + pgpRxMmcmLocked : in sl; + -- Non VC Rx Signals + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType; + -- Non VC Tx Signals + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + -- Frame Transmit Interface - 1 Lane, Array of 4 VCs + pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + -- Frame Receive Interface - 1 Lane, Array of 4 VCs + pgpRxMasters : out AxiStreamMasterArray(3 downto 0); + pgpRxMasterMuxed : out AxiStreamMasterType; + pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0); + -- AXI-Lite DRP interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); +end Pgp2fcGthUltra; + +architecture mapping of Pgp2fcGthUltra is + + signal resetGtSync : sl; + signal gtHardReset : sl; + + -- PgpRx Signals + signal resetRxSync : sl; + signal gtRxUserReset : sl; + signal phyRxLaneIn : Pgp2fcRxPhyLaneInType; + signal phyRxReady : sl; + signal phyRxInit : sl; + + -- PgpTx Signals + signal gtTxUserReset : sl := '0'; + signal phyTxLaneOut : Pgp2fcTxPhyLaneOutType; + signal phyTxReady : sl; + + signal phyRxInitSync : sl; + +begin + + pgpTxResetDone <= phyTxReady; + pgpRxResetDone <= phyRxReady; + + U_RstSync_1 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpTxIn.resetGt, -- [in] + clk => stableClk, -- [in] + rstOut => resetGtSync); -- [out] + + --gtHardReset <= resetGtSync or stableRst; + gtHardReset <= stableRst; + + U_RstSync_4 : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => phyRxInitSync); -- [out] + + -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset + U_RstSync_2 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpRxIn.resetRx, -- [in] + clk => stableClk, -- [in] + rstOut => resetRxSync); -- [out] + + gtRxUserReset <= phyRxInitSync or resetRxSync; + + U_RstSync_3 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpTxIn.resetTx, -- [in] + clk => stableClk, -- [in] + rstOut => gtTxUserReset); -- [out] + + U_Pgp2fcLane : entity surf.Pgp2fcLane + generic map ( + FC_WORDS_G => FC_WORDS_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, + NUM_VC_EN_G => NUM_VC_EN_G, + TX_ENABLE_G => TX_ENABLE_G, + RX_ENABLE_G => RX_ENABLE_G) + port map ( + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxReset, + pgpTxIn => pgpTxIn, + pgpTxOut => pgpTxOut, + pgpTxMasters => pgpTxMasters, + pgpTxSlaves => pgpTxSlaves, + phyTxLaneOut => phyTxLaneOut, + phyTxReady => phyTxReady, + pgpRxClk => pgpRxClk, + pgpRxClkRst => pgpRxReset, + pgpRxIn => pgpRxIn, + pgpRxOut => pgpRxOut, + pgpRxMasters => pgpRxMasters, + pgpRxMasterMuxed => pgpRxMasterMuxed, + pgpRxCtrl => pgpRxCtrl, + phyRxLaneIn => phyRxLaneIn, + phyRxReady => phyRxReady, + phyRxInit => phyRxInit); + + -------------------------- + -- Wrapper for GTH IP core + -------------------------- + PgpGthCoreWrapper_1 : entity surf.Pgp2fcGthCoreWrapper + generic map ( + TPD_G => TPD_G, + SEL_FABRIC_REFCLK_G => SEL_FABRIC_REFCLK_G, + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) + port map ( + stableClk => stableClk, + stableRst => gtHardReset, + gtRefClk => gtRefClk, + gtFabricRefClk => gtFabricRefClk, + gtUserRefClk => gtUserRefClk, + gtRxP => pgpGtRxP, + gtRxN => pgpGtRxN, + gtTxP => pgpGtTxP, + gtTxN => pgpGtTxN, + rxReset => gtRxUserReset, + rxUsrClkActive => pgpRxMmcmLocked, + rxResetDone => phyRxReady, + rxPmaResetDone => pgpRxPmaResetDone, + rxUsrClk => pgpRxClk, + rxData => phyRxLaneIn.data, + rxDataK => phyRxLaneIn.dataK, + rxDispErr => phyRxLaneIn.dispErr, + rxDecErr => phyRxLaneIn.decErr, + rxPolarity => RX_POLARITY_G, + rxOutClk => pgpRxOutClk, + rxRecClk => rxRecClk, + txReset => gtTxUserReset, + txUsrClk => pgpTxClk, + txUsrClkActive => pgpTxMmcmLocked, + txResetDone => phyTxReady, + txData => phyTxLaneOut.data, + txDataK => phyTxLaneOut.dataK, + txPolarity => TX_POLARITY_G, + txOutClk => pgpTxOutClk, + loopback => pgpRxIn.loopback, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl new file mode 100644 index 0000000000..ea9f88635c --- /dev/null +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl @@ -0,0 +1,14 @@ +# Load RUCKUS library +source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_PROC_TCL) + +# Load local source Code and constraints +if { $::env(VIVADO_VERSION) >= 2020.1 } { + + loadSource -lib surf -dir "$::DIR_PATH/rtl" + + #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" + loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" + +} else { + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" +} From 1b3338a77105520d05e2fae26cddc78bae9f2f62 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 13:51:18 -0700 Subject: [PATCH 31/86] Update to match GTY --- .../gthUltraScale+/ip/Pgp2fcGthCore.xci | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci index 7204351628..96304cc60d 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -768,9 +768,9 @@ "C_RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_CC_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_M_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_M_VAL": [ { "value": "\"1010000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_M_VAL": [ { "value": "\"1001111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_P_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_P_VAL": [ { "value": "\"0101111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_P_VAL": [ { "value": "\"0110000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_DATA_DECODING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -821,19 +821,6 @@ "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "zynquplus" } ], - "BASE_BOARD_PART": [ { "value": "" } ], - "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xck26" } ], - "PACKAGE": [ { "value": "sfvc784" } ], - "PREFHDL": [ { "value": "VHDL" } ], - "SILICON_REVISION": [ { "value": "" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], - "SPEEDGRADE": [ { "value": "-2LV" } ], - "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "C" } ] - }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], @@ -926,4 +913,4 @@ } } } -} \ No newline at end of file +} From 92206c62c9e2c38ca5fb735beeafb1f10142fa42 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 12 Jun 2024 15:32:47 -0700 Subject: [PATCH 32/86] Load both GTH and GTY --- protocols/pgp/pgp2fc/ruckus.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/ruckus.tcl b/protocols/pgp/pgp2fc/ruckus.tcl index ec2b8d8d31..a542b35935 100644 --- a/protocols/pgp/pgp2fc/ruckus.tcl +++ b/protocols/pgp/pgp2fc/ruckus.tcl @@ -15,8 +15,8 @@ if { ${family} eq {artix7} } { if { ${family} eq {kintexuplus} || ${family} eq {zynquplus} || ${family} eq {zynquplusRFSOC} } { - # loadRuckusTcl "$::DIR_PATH/gthUltraScale+" - loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" + loadRuckusTcl "$::DIR_PATH/gthUltraScale+" + loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" } if { ${family} eq {virtexuplus} || From 2181b8948bd131d2b81c09fc9c26e91d978fea9f Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 20 Jun 2024 15:05:14 -0700 Subject: [PATCH 33/86] align checker: check default axiclkfreq --- xilinx/general/rtl/GtRxAlignCheck.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index ea07181ada..43318e2e37 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -26,7 +26,7 @@ entity GtRxAlignCheck is generic ( TPD_G : time := 1 ns; GT_TYPE_G : string := "GTHE3"; -- or GTYE3, GTHE4, GTYE4 - AXI_CLK_FREQ_G : real := 125.0e6; + AXI_CLK_FREQ_G : real := 156.25e6; DRP_ADDR_G : slv(31 downto 0)); port ( -- Clock Monitoring From bc67c6176629315b5f9cf31ab40485e397de666a Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 20 Jun 2024 16:22:13 -0700 Subject: [PATCH 34/86] align checker: add simulation bypass option --- xilinx/general/rtl/GtRxAlignCheck.vhd | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index 43318e2e37..e991a0bf35 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -24,9 +24,12 @@ use surf.AxiLitePkg.all; entity GtRxAlignCheck is generic ( - TPD_G : time := 1 ns; - GT_TYPE_G : string := "GTHE3"; -- or GTYE3, GTHE4, GTYE4 - AXI_CLK_FREQ_G : real := 156.25e6; + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + LOCK_VALUE_G : integer := 16; + MASK_VALUE_G : integer := 126; + GT_TYPE_G : string := "GTHE3"; -- or GTYE3, GTHE4, GTYE4 + AXI_CLK_FREQ_G : real := 156.25e6; DRP_ADDR_G : slv(31 downto 0)); port ( -- Clock Monitoring @@ -65,9 +68,6 @@ architecture rtl of GtRxAlignCheck is constant COMMA_ALIGN_LATENCY_OFFSET_C : slv(31 downto 0) := ite((GT_TYPE_G = "GTHE3"), x"0000_0540", x"0000_0940"); constant COMMA_ALIGN_LATENCY_ADDR_C : slv(31 downto 0) := (DRP_ADDR_G + COMMA_ALIGN_LATENCY_OFFSET_C); - constant LOCK_VALUE_C : integer := 16; - constant MASK_VALUE_C : integer := 126; - type StateType is ( RESET_S, READ_S, @@ -95,12 +95,12 @@ architecture rtl of GtRxAlignCheck is locked => '0', rst => '1', rstRetryCnt => '0', - override => '0', + override => toSl(SIMULATION_G), rstlen => toSlv(3, 4), rstcnt => toSlv(0, 4), retryCnt => toSlv(0, 16), - tgt => toSlv(LOCK_VALUE_C, 7), - mask => toSlv(MASK_VALUE_C, 7), + tgt => toSlv(LOCK_VALUE_G, 7), + mask => toSlv(MASK_VALUE_G, 7), last => toSlv(0, 16), sample => (others => (others => '0')), sAxilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, From 7ac4c7f6aa2cdded6171e009902194945521345b Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 24 Jun 2024 15:30:00 -0700 Subject: [PATCH 35/86] update ip core (point gt to the correct quad) --- .../gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 +- .../gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 38 +++++++++---------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index b705a004c6..a75891e3e3 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:44598e02aeab4733c5c014c81bf55c67b402f5340221ca793d1c43a8699c80c0 -size 313487 +oid sha256:ab34660c08b2688470649a056d02a2fe1722f760d8d90f5a669d04a267829fa2 +size 313219 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index d7b7ede705..7565876947 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -4,7 +4,7 @@ "xci_name": "Pgp2fcGtyCore", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", "ip_revision": "16", - "gen_directory": "../../../../TrackerPcieBittware_project.gen/sources_1/ip/Pgp2fcGtyCore", + "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore", "parameters": { "component_parameters": { "GT_TYPE": [ { "value": "GTY", "resolve_type": "user", "usage": "all" } ], @@ -13,9 +13,9 @@ "GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ], "RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], "TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], - "CHANNEL_ENABLE": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "TX_MASTER_CHANNEL": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "RX_MASTER_CHANNEL": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "CHANNEL_ENABLE": [ { "value": "X0Y20", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_MASTER_CHANNEL": [ { "value": "X0Y20", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_MASTER_CHANNEL": [ { "value": "X0Y20", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "LOCATE_COMMON": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -156,8 +156,8 @@ "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "RX_REFCLK_SOURCE": [ { "value": "X0Y4 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "TX_REFCLK_SOURCE": [ { "value": "X0Y4 clk1+2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], "LOCATE_RESET_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ], "LOCATE_TX_BUFFER_BYPASS_CONTROLLER": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ], @@ -728,7 +728,7 @@ "Component_Name": [ { "value": "Pgp2fcGtyCore", "value_src": "user", "resolve_type": "user", "usage": "all" } ] }, "model_parameters": { - "C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_CHANNEL_ENABLE": [ { "value": "\"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_PCIE_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -775,7 +775,7 @@ "C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_LINE_RATE": [ { "value": "3.7142857", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_RX_MASTER_CHANNEL_IDX": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_MASTER_CHANNEL_IDX": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_OUTCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_RX_OUTCLK_SOURCE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -806,7 +806,7 @@ "C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TX_LINE_RATE": [ { "value": "3.7142857", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_TX_MASTER_CHANNEL_IDX": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_MASTER_CHANNEL_IDX": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_TX_OUTCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_TX_OUTCLK_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -825,7 +825,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "16" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../TrackerPcieBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ], + "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2023.1" } ], @@ -856,26 +856,26 @@ "gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], - "cplllockdetclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "cplllocken_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ], - "cpllrefclksel_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x1" } ], + "cplllockdetclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cplllocken_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllrefclksel_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "drpen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "drpwe_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtrefclk0_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtyrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtyrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "loopback_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "rx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxcdrreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "rxcdrreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxcommadeten_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxmcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], @@ -883,8 +883,8 @@ "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], - "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], From a356df01ec0d979ce8e5250c25843ed819d04a88 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 19 Jul 2024 12:49:19 -0700 Subject: [PATCH 36/86] propagate simulation generic --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 ++ protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 1 + 2 files changed, 3 insertions(+) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 6cd9bcd6e5..ccd6af52cb 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity Pgp2fcGtyCoreWrapper is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; SEL_FABRIC_REFCLK_G : boolean := false; USE_ALIGN_CHECK_G : boolean := true; AXI_CLK_FREQ_G : real := 125.0e6; @@ -384,6 +385,7 @@ begin U_AlignCheck : entity surf.GtRxAlignCheck generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, GT_TYPE_G => "GTYE4", AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 8b4b6d7f5a..a2b6decf11 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -193,6 +193,7 @@ begin PgpGtyCoreWrapper_1 : entity surf.Pgp2fcGtyCoreWrapper generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, SEL_FABRIC_REFCLK_G => SEL_FABRIC_REFCLK_G, AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) From ff71a9b7170bf10c9d34bb02bea445a294a2c6ba Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 23 Jul 2024 17:25:55 -0700 Subject: [PATCH 37/86] add back stableRst to reset_all --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index ccd6af52cb..c35a4d5a8b 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -257,7 +257,7 @@ begin gtwiz_userclk_tx_active_in(0) => txUsrActive, gtwiz_userclk_rx_active_in(0) => rxUsrActive, gtwiz_reset_clk_freerun_in(0) => stableClk, - gtwiz_reset_all_in(0) => '0', + gtwiz_reset_all_in(0) => stableRst, gtwiz_buffbypass_tx_reset_in(0) => buffBypassTxReset, gtwiz_buffbypass_tx_start_user_in(0) => buffBypassTxStart, gtwiz_buffbypass_tx_done_out(0) => buffBypassTxDone, From 113c8582342437178a89a5c3b7a1a11720ce4c21 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Tue, 23 Jul 2024 17:49:50 -0700 Subject: [PATCH 38/86] drive reset_all_in properly --- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index a2b6decf11..b8dde55759 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -126,8 +126,8 @@ begin clk => stableClk, -- [in] rstOut => resetGtSync); -- [out] - --gtHardReset <= resetGtSync or stableRst; - gtHardReset <= stableRst; + gtHardReset <= resetGtSync or stableRst; + --gtHardReset <= stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( From 0154399f09019e7cda77b19adf9e18461cf0ea70 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 9 Aug 2024 14:16:43 -0700 Subject: [PATCH 39/86] GTH updates --- .../pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd | 2 ++ protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 1 + protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl | 4 ++-- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index aeb636b3ca..32dc6baca1 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity Pgp2fcGthCoreWrapper is generic ( TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; SEL_FABRIC_REFCLK_G : boolean := false; USE_ALIGN_CHECK_G : boolean := true; AXI_CLK_FREQ_G : real := 125.0e6; @@ -384,6 +385,7 @@ begin U_AlignCheck : entity surf.GtRxAlignCheck generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, GT_TYPE_G => "GTHE4", AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index 125062768b..b282493271 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -193,6 +193,7 @@ begin PgpGthCoreWrapper_1 : entity surf.Pgp2fcGthCoreWrapper generic map ( TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, SEL_FABRIC_REFCLK_G => SEL_FABRIC_REFCLK_G, AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl index ea9f88635c..9c3648427a 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl @@ -6,8 +6,8 @@ if { $::env(VIVADO_VERSION) >= 2020.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" - #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" - loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" + loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" + #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" } else { puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" From 91c7d12115a6f85736780893054b89b358db0d17 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Wed, 21 Aug 2024 14:43:07 -0700 Subject: [PATCH 40/86] opt reset --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd | 4 +++- .../gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 11 ++++++++--- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 4 ++-- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd index a01be22242..8a8b939275 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd @@ -87,6 +87,7 @@ architecture Pgp2fcRx of Pgp2fcRx is signal overflow : slv(3 downto 0); signal intFcValid : sl; signal intFcError : sl; + signal phyRxRst : sl; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of @@ -101,6 +102,7 @@ begin pgpRxOut.phyRxReady <= phyRxReady; pgpRxOut.remOverflow <= overflow; pgpRxOut.remPause <= pause; + phyRxRst <= '0'; -- Interface connection intPhyRxData <= phyRxLaneIn.data; @@ -117,7 +119,7 @@ begin ) port map ( pgpRxClkEn => pgpRxClkEn, pgpRxClk => pgpRxClk, - pgpRxClkRst => pgpRxClkRst, + pgpRxClkRst => phyRxRst, pgpRxLinkReady => intRxLinkReady, pgpRxLinkDown => pgpRxOut.linkDown, pgpRxLinkError => pgpRxOut.linkError, diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index c35a4d5a8b..f09b241a55 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -50,6 +50,7 @@ entity Pgp2fcGtyCoreWrapper is gtTxN : out sl; -- Rx ports + phyRxReady : out sl; rxReset : in sl; rxUsrClkActive : in sl; rxResetDone : out sl; @@ -212,7 +213,8 @@ architecture mapping of Pgp2fcGtyCoreWrapper is signal rxPmaReset : sl := '0'; signal txPcsReset : sl := '0'; signal txPmaReset : sl := '0'; - signal rxPmaResetDoneInt : sl := '0'; + signal rxPmaResetDoneInt : sl := '0'; + signal rxResetDoneInt : sl := '0'; signal txPmaResetDone : sl := '0'; signal rxByteIsAligned : sl := '0'; signal rxByteReAlign : sl := '0'; @@ -331,7 +333,7 @@ begin rxrecclkout_out(0) => rxRecClk, txoutclk_out(0) => txOutClkGt, -- unused rxpmaresetdone_out(0) => rxPmaResetDoneInt, - rxresetdone_out(0) => rxResetDone, + rxresetdone_out(0) => rxResetDoneInt, rxsyncdone_out(0) => rxSyncDone, txpmaresetdone_out(0) => txPmaResetDone, txresetdone_out(0) => txResetDone); @@ -443,7 +445,10 @@ begin txUsrActive <= txUsrClkActive and txPmaResetDone; rxUsrActive <= rxUsrClkActive and rxPmaResetDoneInt; - rxPmaResetDone <= rxPmaResetDoneInt; + rxPmaResetDone <= rxPmaResetDoneInt; + + rxResetDone <= rxResetDoneInt and buffBypassRxDone; + phyRxReady <= rxResetDoneInt; cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index b8dde55759..c044d93ed7 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -127,7 +127,6 @@ begin rstOut => resetGtSync); -- [out] gtHardReset <= resetGtSync or stableRst; - --gtHardReset <= stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( @@ -207,9 +206,10 @@ begin gtRxN => pgpGtRxN, gtTxP => pgpGtTxP, gtTxN => pgpGtTxN, + phyRxReady => phyRxReady, rxReset => gtRxUserReset, rxUsrClkActive => pgpRxMmcmLocked, - rxResetDone => phyRxReady, + rxResetDone => pgpRxResetDone, rxPmaResetDone => pgpRxPmaResetDone, rxUsrClk => pgpRxClk, rxData => phyRxLaneIn.data, From 33ce911f893912a2de1074273b6e850913b65fde Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 23 Aug 2024 10:07:49 -0700 Subject: [PATCH 41/86] fix multi-driven net --- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 1 - 1 file changed, 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index c044d93ed7..83b84c21bd 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -115,7 +115,6 @@ architecture mapping of Pgp2fcGtyUltra is begin pgpTxResetDone <= phyTxReady; - pgpRxResetDone <= phyRxReady; U_RstSync_1 : entity surf.PwrUpRst generic map ( From 1c56abfa9b589f4b5f9d857cfa6d260e5f671522 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 5 Sep 2024 16:27:20 -0700 Subject: [PATCH 42/86] update rst --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd | 2 ++ protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd | 3 ++- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd index 0b0df8210a..83ec8425a9 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd @@ -68,6 +68,7 @@ entity Pgp2fcLane is pgpRxClkEn : in sl := '1'; pgpRxClk : in sl := '0'; pgpRxClkRst : in sl := '0'; + pgpRxPhyRst : in sl := '0'; -- Non-VC related IO pgpRxIn : in Pgp2fcRxInType := PGP2FC_RX_IN_INIT_C; @@ -152,6 +153,7 @@ begin pgpRxClkEn => pgpRxClkEn, pgpRxClk => pgpRxClk, pgpRxClkRst => pgpRxClkRst, + pgpRxPhyRst => pgpRxPhyRst, pgpRxIn => pgpRxIn, pgpRxOut => intRxOut, pgpRxMaster => intRxMaster, diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd index 8a8b939275..2584a80327 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd @@ -38,6 +38,7 @@ entity Pgp2fcRx is pgpRxClkEn : in sl := '1'; -- Master clock enable pgpRxClk : in sl; -- Master clock pgpRxClkRst : in sl; -- Synchronous reset input + pgpRxPhyRst : in sl := '0'; -- Non-VC related IO pgpRxIn : in Pgp2fcRxInType; @@ -102,7 +103,7 @@ begin pgpRxOut.phyRxReady <= phyRxReady; pgpRxOut.remOverflow <= overflow; pgpRxOut.remPause <= pause; - phyRxRst <= '0'; + phyRxRst <= pgpRxPhyRst; -- Interface connection intPhyRxData <= phyRxLaneIn.data; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 83b84c21bd..4695e1c3f4 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -176,6 +176,7 @@ begin phyTxReady => phyTxReady, pgpRxClk => pgpRxClk, pgpRxClkRst => pgpRxReset, + pgpRxPhyRst => gtRxUserReset, pgpRxIn => pgpRxIn, pgpRxOut => pgpRxOut, pgpRxMasters => pgpRxMasters, From 6dae9bc745f060d6332faa5ddd44dfff55a812d8 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 10 Sep 2024 11:24:37 -0700 Subject: [PATCH 43/86] Fix multi-defined groups. Caused by bad merge --- python/surf/axi/_AxiVersion.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/python/surf/axi/_AxiVersion.py b/python/surf/axi/_AxiVersion.py index 4b4e788c4d..79f2f11379 100644 --- a/python/surf/axi/_AxiVersion.py +++ b/python/surf/axi/_AxiVersion.py @@ -96,7 +96,6 @@ def parseUpTime(var,read): base = pr.UInt, mode = 'RW', hidden = True, - groups = 'NoConfig' )) self.add(pr.RemoteCommand( @@ -137,7 +136,6 @@ def FpgaReloadAtAddress(arg): bitOffset = 0x00, base = pr.UInt, mode = 'RW', - groups = 'NoConfig', )) @self.command(description = 'Toggle UserReset') From 3f5b42ef1a3979f7bdd8bbfc04307fcf4b874391 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 16 Sep 2024 17:25:34 -0700 Subject: [PATCH 44/86] purge rxrecclk; rtl update --- .../pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd | 3 --- protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 2 -- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 3 --- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 2 -- 4 files changed, 10 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index 32dc6baca1..c3e88c0928 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -61,7 +61,6 @@ entity Pgp2fcGthCoreWrapper is rxDecErr : out slv(1 downto 0); rxPolarity : in sl; rxOutClk : out sl; - rxRecClk : out sl; -- raw recovered clock -- Tx Ports txReset : in sl; @@ -159,7 +158,6 @@ architecture mapping of Pgp2fcGthCoreWrapper is rxctrl3_out : out std_logic_vector (7 downto 0); rxdlysresetdone_out : out std_logic_vector (0 downto 0); rxoutclk_out : out std_logic_vector (0 downto 0); - rxrecclkout_out : out std_logic_vector (0 downto 0); rxphaligndone_out : out std_logic_vector (0 downto 0); rxpmaresetdone_out : out std_logic_vector (0 downto 0); rxresetdone_out : out std_logic_vector (0 downto 0); @@ -328,7 +326,6 @@ begin rxdlysresetdone_out(0) => rxDlysResetDone, rxphaligndone_out(0) => rxPhyAlignDone, rxoutclk_out(0) => rxOutClkGt, - rxrecclkout_out(0) => rxRecClk, txoutclk_out(0) => txOutClkGt, -- unused rxpmaresetdone_out(0) => rxPmaResetDoneInt, rxresetdone_out(0) => rxResetDone, diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index b282493271..260b2e8897 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -52,7 +52,6 @@ entity Pgp2fcGthUltra is gtRefClk : in sl; gtFabricRefClk : in sl; gtUserRefClk : in sl; - rxRecClk : out sl; -- Gt Serial IO pgpGtTxP : out sl; pgpGtTxN : out sl; @@ -218,7 +217,6 @@ begin rxDecErr => phyRxLaneIn.decErr, rxPolarity => RX_POLARITY_G, rxOutClk => pgpRxOutClk, - rxRecClk => rxRecClk, txReset => gtTxUserReset, txUsrClk => pgpTxClk, txUsrClkActive => pgpTxMmcmLocked, diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index f09b241a55..dac9745295 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -62,7 +62,6 @@ entity Pgp2fcGtyCoreWrapper is rxDecErr : out slv(1 downto 0); rxPolarity : in sl; rxOutClk : out sl; - rxRecClk : out sl; -- raw recovered clock -- Tx Ports txReset : in sl; @@ -160,7 +159,6 @@ architecture mapping of Pgp2fcGtyCoreWrapper is rxctrl3_out : out std_logic_vector (7 downto 0); rxdlysresetdone_out : out std_logic_vector (0 downto 0); rxoutclk_out : out std_logic_vector (0 downto 0); - rxrecclkout_out : out std_logic_vector (0 downto 0); rxphaligndone_out : out std_logic_vector (0 downto 0); rxpmaresetdone_out : out std_logic_vector (0 downto 0); rxresetdone_out : out std_logic_vector (0 downto 0); @@ -330,7 +328,6 @@ begin rxdlysresetdone_out(0) => rxDlysResetDone, rxphaligndone_out(0) => rxPhyAlignDone, rxoutclk_out(0) => rxOutClkGt, - rxrecclkout_out(0) => rxRecClk, txoutclk_out(0) => txOutClkGt, -- unused rxpmaresetdone_out(0) => rxPmaResetDoneInt, rxresetdone_out(0) => rxResetDoneInt, diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 4695e1c3f4..3c62d07115 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -52,7 +52,6 @@ entity Pgp2fcGtyUltra is gtRefClk : in sl; gtFabricRefClk : in sl; gtUserRefClk : in sl; - rxRecClk : out sl; -- Gt Serial IO pgpGtTxP : out sl; pgpGtTxN : out sl; @@ -218,7 +217,6 @@ begin rxDecErr => phyRxLaneIn.decErr, rxPolarity => RX_POLARITY_G, rxOutClk => pgpRxOutClk, - rxRecClk => rxRecClk, txReset => gtTxUserReset, txUsrClk => pgpTxClk, txUsrClkActive => pgpTxMmcmLocked, From 417d460ad3bae1c464da3f5bdfe332f7d35fb42f Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Mon, 16 Sep 2024 17:51:33 -0700 Subject: [PATCH 45/86] purge rxrecclk; update ip-cores --- .../pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 ++-- .../pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 15 +++++++-------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index a75891e3e3..3eb1439baf 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab34660c08b2688470649a056d02a2fe1722f760d8d90f5a669d04a267829fa2 -size 313219 +oid sha256:c16c0c09f624142fc5832b19fc5f50a64d534138217d7917cfd72b79db013c28 +size 269996 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index 7565876947..aad2bc36e8 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -3,7 +3,7 @@ "ip_inst": { "xci_name": "Pgp2fcGtyCore", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", - "ip_revision": "16", + "ip_revision": "18", "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore", "parameters": { "component_parameters": { @@ -155,7 +155,7 @@ "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], @@ -170,10 +170,10 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "28", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "43", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "15", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -823,12 +823,12 @@ }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "16" } ], + "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2023.1" } ], + "SWVERSION": [ { "value": "2024.1" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, @@ -907,7 +907,6 @@ "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], From a4a8840a46aa36735355a1064f454ab7d7887a7b Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Wed, 25 Sep 2024 14:36:43 -0700 Subject: [PATCH 46/86] switch pgp2fc cores drp freq config to gtRefClk-div-2 (185.714/2 MHz) --- .../gthUltraScale+/ip/Pgp2fcGthCore.dcp | 4 +- .../gthUltraScale+/ip/Pgp2fcGthCore.xci | 102 +++++++++--------- .../gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 +- .../gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 10 +- 4 files changed, 60 insertions(+), 60 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp index 94986d2380..6689d44e94 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:22e243c27bc43679a281ba0094d67ec10d60a8ecc38d454d6dcbe3ba5d445ea0 -size 313652 +oid sha256:b6e9de34d1bb58787665959d24cd27cdcaa10978d81a6ab105c347d3f083a25a +size 268308 diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci index 96304cc60d..786ad0a031 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -3,7 +3,7 @@ "ip_inst": { "xci_name": "Pgp2fcGthCore", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", - "ip_revision": "16", + "ip_revision": "18", "gen_directory": "../../../../zCCM_kria_project.gen/sources_1/ip/Pgp2fcGthCore", "parameters": { "component_parameters": { @@ -23,32 +23,32 @@ "INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], "INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], - "RX_PPM_OFFSET": [ { "value": "200", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "INS_LOSS_NYQ": [ { "value": "14", "resolve_type": "user", "format": "float", "usage": "all" } ], + "INS_LOSS_NYQ": [ { "value": "14", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ], "PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], "TX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "TX_PLL_TYPE": [ { "value": "CPLL", "resolve_type": "user", "usage": "all" } ], + "TX_PLL_TYPE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "TX_DATA_ENCODING": [ { "value": "8B10B", "resolve_type": "user", "usage": "all" } ], - "TX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], - "TX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_DATA_ENCODING": [ { "value": "8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_USER_DATA_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_INT_DATA_WIDTH": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "TX_OUTCLK_SOURCE": [ { "value": "TXPLLREFCLK_DIV1", "resolve_type": "user", "usage": "all" } ], + "TX_OUTCLK_SOURCE": [ { "value": "TXPLLREFCLK_DIV1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ], "RX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RX_PLL_TYPE": [ { "value": "CPLL", "resolve_type": "user", "usage": "all" } ], + "RX_PLL_TYPE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RX_DATA_DECODING": [ { "value": "8B10B", "resolve_type": "user", "usage": "all" } ], - "RX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], - "RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_DATA_DECODING": [ { "value": "8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_USER_DATA_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_INT_DATA_WIDTH": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], - "RX_JTOL_FC": [ { "value": "2.2281258", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_JTOL_FC": [ { "value": "2.2281258", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_OUTCLK_SOURCE": [ { "value": "RXOUTCLKPMA", "resolve_type": "user", "usage": "all" } ], "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -62,15 +62,15 @@ "RX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "RX_COMMA_PRESET": [ { "value": "K28.5", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_PRESET": [ { "value": "K28.5", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_COMMA_VALID_ONLY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], - "RX_COMMA_P_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "RX_COMMA_M_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_COMMA_P_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_COMMA_M_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "usage": "all" } ], "RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "usage": "all" } ], - "RX_COMMA_MASK": [ { "value": "1111111111", "resolve_type": "user", "usage": "all" } ], - "RX_COMMA_ALIGN_WORD": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_COMMA_MASK": [ { "value": "1111111111", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_ALIGN_WORD": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_SLIDE_MODE": [ { "value": "OFF", "resolve_type": "user", "usage": "all" } ], "RX_CB_NUM_SEQ": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], @@ -168,7 +168,7 @@ "LOCATE_USER_DATA_WIDTH_SIZING": [ { "value": "CORE", "resolve_type": "user", "usage": "all" } ], "ORGANIZE_PORTS_BY": [ { "value": "NAME", "resolve_type": "user", "enabled": false, "usage": "all" } ], "PRESET": [ { "value": "GTH-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "resolve_type": "user", "usage": "all" } ], + "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], @@ -180,10 +180,10 @@ "SECONDARY_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "92.857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "92.857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "57", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -768,9 +768,9 @@ "C_RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_CC_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_M_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_M_VAL": [ { "value": "\"1001111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_M_VAL": [ { "value": "\"1010000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_P_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_P_VAL": [ { "value": "\"0110000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_P_VAL": [ { "value": "\"0101111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_DATA_DECODING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -823,12 +823,12 @@ }, "runtime_parameters": { "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "16" } ], + "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], "OUTPUTDIR": [ { "value": "../../../../zCCM_kria_project.gen/sources_1/ip/Pgp2fcGthCore" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2023.1" } ], + "SWVERSION": [ { "value": "2024.1" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } }, @@ -856,33 +856,33 @@ "gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], - "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0x00000" } ], - "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x00000000" } ], - "drpen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "drpwe_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], + "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drpen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpwe_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gthrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gthrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "gtrefclk0_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "loopback_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x00" } ], - "rx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxcdrreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxcommadeten_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxmcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxpcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "gtrefclk0_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "loopback_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "rx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcdrreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcommadeten_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxmcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "tx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], - "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ], - "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], - "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "tx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "cpllfbclklost_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], @@ -913,4 +913,4 @@ } } } -} +} \ No newline at end of file diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index 3eb1439baf..f4ab0c0738 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c16c0c09f624142fc5832b19fc5f50a64d534138217d7917cfd72b79db013c28 -size 269996 +oid sha256:316338e899e3d38e2d24a9c6003546b683f0799546dd30426e942d97d4ff0ad3 +size 269500 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index aad2bc36e8..8c6c4966ee 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -170,10 +170,10 @@ "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "43", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "25", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], - "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "15", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "11", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], "INTERNAL_UPDATE_IP_SYMBOL_drpclk_in": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "SECONDARY_QPLL_LINE_RATE": [ { "value": "10.3125", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "92.857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "92.857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], From 5f8e4528e8854ecc8b0518f641ade6358f3aca90 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 26 Sep 2024 14:34:36 -0700 Subject: [PATCH 47/86] moved README.me to SLAC protocol confluence page and updated code header hyperlinks --- protocols/pgp/pgp2fc/README.md | 26 ------------------- .../core/rtl/Pgp2fcAlignmentChecker.vhd | 2 +- .../core/rtl/Pgp2fcAlignmentController.vhd | 2 ++ protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd | 2 +- .../pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd | 2 +- .../pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd | 2 +- protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd | 2 +- .../pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd | 2 +- .../pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd | 2 +- .../pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd | 2 +- .../rtl/Pgp2fcGthCoreWrapper.vhd | 2 +- .../gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 2 +- protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd | 2 +- .../pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd | 2 +- .../rtl/Pgp2fcGtyCoreWrapper.vhd | 2 +- .../gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 2 +- 21 files changed, 21 insertions(+), 45 deletions(-) delete mode 100644 protocols/pgp/pgp2fc/README.md diff --git a/protocols/pgp/pgp2fc/README.md b/protocols/pgp/pgp2fc/README.md deleted file mode 100644 index c6b6875fdc..0000000000 --- a/protocols/pgp/pgp2fc/README.md +++ /dev/null @@ -1,26 +0,0 @@ -# PGP2 Fast Control (PGP2FC) Implementation - -Similar implementation as PGP2B, while giving priority to fast control words and fixed latency. - -Applications need to create the MGT wrapper with no elastic buffers and PMA RX Slide enabled. See LDMX fast control application example. - -Xilinx does NOT allow this configuration directly from the transceiver wizard, but it can be overriden by configurating it with PCS slide and then using the following constraint: - -``` -set_property RXSLIDE_MODE PMA [get_cells {}] -``` - -**This variant only supports a single-lane mode and special care must be taken when using virtual channels and fast control excessively.** - -## Design considerations - -Because fast control has priority over virtual channel data, it is possible that the virtual channels will become starved if too many fast control words are sent frequently or with no break between them. - -Using the fast control scheme in LDMX as an example: - -- Experimental operational clock is 37.2MHz and the link will operate at 3.72GHz with 186MHz on the user side. -- In this scheme, we send a single fast control word every 37.2MHz clock tick with 16-bits width to indicate an edge transition, even if there are no fast control flags to send. -- Because of the experimental clock of 37.2MHz, we can send up to 5 data words in the link (186/37.2=5), and because PGP2FC fast control words have an overhead of 1 word for header and CRC, it means that out of the 5 data words per experimental clock, 2 will be used for fast control. -- Leaving 3/5 available for virtual channel operation. This is be fine for light operation. - -In the example above, if the width of the fast control word got changed from 16-bits to 64-bits, it would mean the link would be saturated and the virtual channels would be starved. In this situation virtual channels should not be used. \ No newline at end of file diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd index fe7b854964..88b3ecd2bc 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentChecker.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd index e85549d87b..1b54d27dc6 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAlignmentController.vhd @@ -1,4 +1,6 @@ ------------------------------------------------------------------------------- +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw +------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- -- Description: GTH RX Byte Alignment Controller diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd index 54ff311b39..b195fc35cd 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd index 83ec8425a9..79d17bfeb9 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd index 272039e8bf..ffce09f03f 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd index 2584a80327..891e04e814 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd index dab3283dac..a3ed41b274 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxCell.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd index 259d88450d..c4273b1535 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd index 8a3d47a04b..146bdf9235 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd index 26d1706f3e..032224fa81 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd index 8b2fe22b4f..9978c308f7 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd index a57aee2bd9..48ae3c84f0 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd b/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd index e849f5ce36..cb21078238 100644 --- a/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd +++ b/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd b/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd index c6902b21d6..9fd38e9f62 100644 --- a/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd +++ b/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index c3e88c0928..c716a23570 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index 260b2e8897..e746fad398 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd index 1af2dd90c3..1add05be55 100644 --- a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd +++ b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd index e22e023cbc..559972b884 100644 --- a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd +++ b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index dac9745295..a9d1c4953a 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 3c62d07115..5697ae7a59 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +-- Title : PGP2fc: https://confluence.slac.stanford.edu/x/JhItHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- From 84dcb34f111ee0ab0754d1c35b88f84746a787fc Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 26 Sep 2024 14:36:13 -0700 Subject: [PATCH 48/86] whitespace removal --- protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index e746fad398..0e909ac6e7 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -126,7 +126,7 @@ begin rstOut => resetGtSync); -- [out] --gtHardReset <= resetGtSync or stableRst; - gtHardReset <= stableRst; + gtHardReset <= stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( From a8cf8a5bb4e5d00774a537d87ad49fdd1f8cdecb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 2 Oct 2024 09:02:23 -0700 Subject: [PATCH 49/86] Add ruckus flag to optionally load XCI instead of DCP for PGP2FC --- protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl index f6668faf6c..3e72744e12 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl @@ -6,7 +6,13 @@ if { $::env(VIVADO_VERSION) >= 2023.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" - loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" + if { [info exists ::env(PGP2FC_XCI)] != 0 && $::env(PGP2FC_XCI) == 1 } { + loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" + puts "Loading XCI file for PGP2FC" + } else { + loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" + } + #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" } else { From 92885911a3646123072bc176bc9e3dff9622b69d Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 2 Oct 2024 23:00:40 -0700 Subject: [PATCH 50/86] Make histogram registers read only --- xilinx/general/rtl/GtRxAlignCheck.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd index e991a0bf35..81fb55c46d 100644 --- a/xilinx/general/rtl/GtRxAlignCheck.vhd +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -185,12 +185,12 @@ begin axiSlaveWaitTxn(axilEp, sAxilWriteMaster, sAxilReadMaster, v.sAxilWriteSlave, v.sAxilReadSlave); for i in 0 to r.sample'length-1 loop - axiSlaveRegister(axilEp, toSlv(4*(i/4), 12), 8*(i mod 4), v.sample(i)); + axiSlaveRegisterR(axilEp, toSlv(4*(i/4), 12), 8*(i mod 4), r.sample(i)); end loop; axiSlaveRegister (axilEp, x"100", 0, v.tgt); axiSlaveRegister (axilEp, x"100", 8, v.mask); axiSlaveRegister (axilEp, x"100", 16, v.rstlen); - axiSlaveRegister (axilEp, x"104", 0, v.last); + axiSlaveRegisterR(axilEp, x"104", 0, r.last); axiSlaveRegisterR(axilEp, x"108", 0, txClkFreq); axiSlaveRegisterR(axilEp, x"10C", 0, rxClkFreq); axiSlaveRegisterR(axilEp, x"110", 0, r.locked); From 7f009031b0955ae2066777218907511e9d52bc42 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 2 Oct 2024 23:00:56 -0700 Subject: [PATCH 51/86] Fix histogram variables --- python/surf/xilinx/_GtRxAlignCheck.py | 47 ++++++++++++--------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py index 2c491c2de6..e835f98679 100644 --- a/python/surf/xilinx/_GtRxAlignCheck.py +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -26,32 +26,6 @@ def __init__( self, # Variables ############################## - # self.addRemoteVariables( - # name = "PhaseCount", - # description = "Timing frame phase", - # offset = 0x00, - # bitSize = 16, - # bitOffset = 0, - # mode = "RO", - # pollInterval = 1, - # number = 128, - # stride = 2, - # hidden = True, - # ) - - self.addRemoteVariables( - name = "PhaseCount", - description = "Timing frame phase", - offset = 0x00, - bitSize = 32, - bitOffset = 0, - mode = "RO", - pollInterval = 1, - number = 64, - stride = 4, - hidden = True, - ) - self.add(pr.RemoteVariable( name = "PhaseTarget", description = "Timing frame phase lock target", @@ -184,3 +158,24 @@ def __init__( self, linkedGet = lambda read: self.RefClkFreqRaw.get(read=read) * 1.0e-6, disp = '{:0.3f}', )) + + self.add(pr.RemoteVariable( + name = "PhaseCount", + description = "Timing frame phase", + offset = 0x00, + valueBits = 8, + valueStride = 8, + numValues = 40, + mode = "RO", + pollInterval = 1, + hidden = False, + )) + + for i in range(40): + self.add(pr.LinkVariable( + name = f'PhaseHist[{i}]', + guiGroup='Hist', + disp = '{:d}', + mode = 'RO', + dependencies = [self.PhaseCount], + linkedGet = lambda read, x=i: self.PhaseCount.get(read=read, index=x))) From 30338570ffa62f36eb508aa7506c920d1acbb8a9 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Thu, 3 Oct 2024 15:45:16 -0700 Subject: [PATCH 52/86] refine resets --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 5 ++--- protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index a9d1c4953a..fe8de319a1 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -449,9 +449,8 @@ begin cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); - rstSyncRxIn <= rxResetAlignCheck or rxReset; - rxResetGt <= rxResetAlignCheck or rxReset; - + rstSyncRxIn <= rxResetAlignCheck; + rxResetGt <= rxResetAlignCheck; txOutClk <= txOutClkB; rxOutClk <= rxOutClkB; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 5697ae7a59..73b9816eec 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -129,7 +129,7 @@ begin U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + PULSE_WIDTH_G => 12500) -- 100us in sim and silicon; otherwise it takes forever to lock port map ( clk => stableClk, -- [in] dataIn => phyRxInit, -- [in] From 31f2bdab08cbc882edd3e84427cb603581610cfd Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 4 Oct 2024 14:17:16 -0700 Subject: [PATCH 53/86] switch to truly stable clock --- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 ++-- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 4 ++-- .../pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 2 -- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 9 +++++---- 4 files changed, 9 insertions(+), 10 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index f4ab0c0738..6fac9fb971 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:316338e899e3d38e2d24a9c6003546b683f0799546dd30426e942d97d4ff0ad3 -size 269500 +oid sha256:a0e5af9d5d2041666461ed0467a0f88b0a6e888f8493b126b4e48278e408b411 +size 269634 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index 8c6c4966ee..6c71764170 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "92.857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "92.857", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index a9d1c4953a..6b5c9283d6 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -35,8 +35,6 @@ entity Pgp2fcGtyCoreWrapper is AXI_CLK_FREQ_G : real := 125.0e6; AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0')); port ( - -- Could use gtUserRefClk instead of stableClk - -- Then change stableRst to extRst stableClk : in sl; stableRst : in sl; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 5697ae7a59..3ba9cf74e7 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -115,10 +115,11 @@ begin pgpTxResetDone <= phyTxReady; + -- assuming a 78.125MHz stableClk U_RstSync_1 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetGt, -- [in] clk => stableClk, -- [in] @@ -129,7 +130,7 @@ begin U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + PULSE_WIDTH_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( clk => stableClk, -- [in] dataIn => phyRxInit, -- [in] @@ -139,7 +140,7 @@ begin U_RstSync_2 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpRxIn.resetRx, -- [in] clk => stableClk, -- [in] @@ -150,7 +151,7 @@ begin U_RstSync_3 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetTx, -- [in] clk => stableClk, -- [in] From b7be13ffc2a45e9563a21075933f6108937ede33 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 12:41:36 -0700 Subject: [PATCH 54/86] Change back to 92.857 MHz freerun frequency Remove project specific outputdir value --- protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci | 2 +- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci index 786ad0a031..5eac4e4d4b 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -825,7 +825,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../zCCM_kria_project.gen/sources_1/ip/Pgp2fcGthCore" } ], + "OUTPUTDIR": [ { "value": "." } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2024.1" } ], diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index 6c71764170..ca08aa91b1 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -183,7 +183,7 @@ "TXPROGDIV_FREQ_SOURCE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], "TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], "SATA_TX_BURST_LEN": [ { "value": "15", "resolve_type": "user", "format": "long", "usage": "all" } ], - "FREERUN_FREQUENCY": [ { "value": "78.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "FREERUN_FREQUENCY": [ { "value": "92.857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], "USER_GTPOWERGOOD_DELAY_EN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "DISABLE_LOC_XDC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -825,7 +825,7 @@ "IPCONTEXT": [ { "value": "IP_Flow" } ], "IPREVISION": [ { "value": "18" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ], + "OUTPUTDIR": [ { "value": "." } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "." } ], "SWVERSION": [ { "value": "2024.1" } ], From a156d1b94de0cb32f4ec11454bec2dd98b8ea08f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 12:52:42 -0700 Subject: [PATCH 55/86] Change path so not project specific --- protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci | 2 +- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci index 5eac4e4d4b..33e068be24 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -4,7 +4,7 @@ "xci_name": "Pgp2fcGthCore", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", "ip_revision": "18", - "gen_directory": "../../../../zCCM_kria_project.gen/sources_1/ip/Pgp2fcGthCore", + "gen_directory": ".", "parameters": { "component_parameters": { "GT_TYPE": [ { "value": "GTH", "resolve_type": "user", "usage": "all" } ], diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index ca08aa91b1..ed74cd34ba 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -4,7 +4,7 @@ "xci_name": "Pgp2fcGtyCore", "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", "ip_revision": "18", - "gen_directory": "../../../../FcHubBittware_project.gen/sources_1/ip/Pgp2fcGtyCore", + "gen_directory": ".", "parameters": { "component_parameters": { "GT_TYPE": [ { "value": "GTY", "resolve_type": "user", "usage": "all" } ], From 47c14391ffd132832fe86f7df19d7ad361715c09 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 12:52:59 -0700 Subject: [PATCH 56/86] Rebuild gty dcp --- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index 6fac9fb971..f4d0713e61 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a0e5af9d5d2041666461ed0467a0f88b0a6e888f8493b126b4e48278e408b411 -size 269634 +oid sha256:e01e8db42b516ac33055c747ad08519c9895d9df75b9d52b2a9872269b84d8f7 +size 269272 From 6a971af6e459f906cf04ce9572aac6a3af75e2ff Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 13:05:08 -0700 Subject: [PATCH 57/86] Rebuild GTH DCP --- protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp index 6689d44e94..b486d6d0d4 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b6e9de34d1bb58787665959d24cd27cdcaa10978d81a6ab105c347d3f083a25a -size 268308 +oid sha256:c314b33708fd6066744d54a39e3a7b930064887035fa04e70461cff709764ea4 +size 268201 From 114c5cf07f7be757e3b854c4d0d355af7b65654f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 13:06:17 -0700 Subject: [PATCH 58/86] Add support for PGPFC_XCI env variable to GTH core --- protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl index 9c3648427a..2a46b90106 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl @@ -6,7 +6,14 @@ if { $::env(VIVADO_VERSION) >= 2020.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" - loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" + if { [info exists ::env(PGP2FC_XCI)] != 0 && $::env(PGP2FC_XCI) == 1 } { + loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" + puts "Loading XCI file for PGP2FC" + } else { + loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" + } + + #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" } else { From 910afb8bc56849548a6bf86c6ad66f5b4480283c Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 13:59:22 -0700 Subject: [PATCH 59/86] Make XCI files alike between GTY and GTH --- .../pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci | 16 +++++++++------- .../pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci | 4 ++-- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci index 33e068be24..289e5b0f63 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.xci @@ -67,8 +67,8 @@ "RX_COMMA_P_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_COMMA_M_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "RX_COMMA_P_VAL": [ { "value": "0101111100", "resolve_type": "user", "usage": "all" } ], - "RX_COMMA_M_VAL": [ { "value": "1010000011", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_P_VAL": [ { "value": "0110000011", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_M_VAL": [ { "value": "1001111100", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_COMMA_MASK": [ { "value": "1111111111", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_COMMA_ALIGN_WORD": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -155,7 +155,7 @@ "RX_CC_VAL_1_3": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], "RX_CC_K_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "RX_CC_DISP_1_3": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "ENABLE_OPTIONAL_PORTS": [ { "value": "drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxrecclkout_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ENABLE_OPTIONAL_PORTS": [ { "value": "cplllockdetclk_in cplllocken_in cpllrefclksel_in drpaddr_in drpclk_in drpdi_in drpen_in drpwe_in gtgrefclk_in loopback_in rxcdrreset_in rxpcsreset_in rxpmareset_in rxpolarity_in txpcsreset_in txpmareset_in txpolarity_in cpllfbclklost_out cplllock_out cpllrefclklost_out drpdo_out drprdy_out rxdlysresetdone_out rxphaligndone_out rxresetdone_out rxsyncdone_out txresetdone_out", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "TX_REFCLK_SOURCE": [ { "value": "", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RX_RECCLK_OUTPUT": [ { "value": "", "resolve_type": "user", "usage": "all" } ], @@ -768,9 +768,9 @@ "C_RX_CC_PERIODICITY": [ { "value": "5000", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_CC_VAL": [ { "value": "\"00000000000000000000000000000000000000000000000000000000000000000000000000000000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_M_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_M_VAL": [ { "value": "\"1010000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_M_VAL": [ { "value": "\"1001111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_COMMA_P_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RX_COMMA_P_VAL": [ { "value": "\"0101111100\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_RX_COMMA_P_VAL": [ { "value": "\"0110000011\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_RX_DATA_DECODING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -856,6 +856,9 @@ "gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "cplllockdetclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cplllocken_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllrefclksel_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], @@ -904,7 +907,6 @@ "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], @@ -913,4 +915,4 @@ } } } -} \ No newline at end of file +} diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci index ed74cd34ba..ae23574f79 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -734,7 +734,7 @@ "C_COMMON_SCALING_FACTOR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CPLL_VCO_FREQUENCY": [ { "value": "3714.2857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_FORCE_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_FREERUN_FREQUENCY": [ { "value": "78.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_FREERUN_FREQUENCY": [ { "value": "92.857", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_GT_TYPE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_GT_REV": [ { "value": "67", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_INCLUDE_CPLL_CAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -915,4 +915,4 @@ } } } -} \ No newline at end of file +} From 94095919f54fe4f1b08bf3d5b8a58d24bbab6ccb Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 13:59:34 -0700 Subject: [PATCH 60/86] Make GTH wrappers match GTY --- .../gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd | 16 +++++++++------- .../pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 16 ++++++++-------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index c716a23570..4dd2d6b469 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -35,8 +35,6 @@ entity Pgp2fcGthCoreWrapper is AXI_CLK_FREQ_G : real := 125.0e6; AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0')); port ( - -- Could use gtUserRefClk instead of stableClk - -- Then change stableRst to extRst stableClk : in sl; stableRst : in sl; @@ -50,6 +48,7 @@ entity Pgp2fcGthCoreWrapper is gtTxN : out sl; -- Rx ports + phyRxReady : out sl; rxReset : in sl; rxUsrClkActive : in sl; rxResetDone : out sl; @@ -210,7 +209,8 @@ architecture mapping of Pgp2fcGthCoreWrapper is signal rxPmaReset : sl := '0'; signal txPcsReset : sl := '0'; signal txPmaReset : sl := '0'; - signal rxPmaResetDoneInt : sl := '0'; + signal rxPmaResetDoneInt : sl := '0'; + signal rxResetDoneInt : sl := '0'; signal txPmaResetDone : sl := '0'; signal rxByteIsAligned : sl := '0'; signal rxByteReAlign : sl := '0'; @@ -255,7 +255,7 @@ begin gtwiz_userclk_tx_active_in(0) => txUsrActive, gtwiz_userclk_rx_active_in(0) => rxUsrActive, gtwiz_reset_clk_freerun_in(0) => stableClk, - gtwiz_reset_all_in(0) => '0', + gtwiz_reset_all_in(0) => stableRst, gtwiz_buffbypass_tx_reset_in(0) => buffBypassTxReset, gtwiz_buffbypass_tx_start_user_in(0) => buffBypassTxStart, gtwiz_buffbypass_tx_done_out(0) => buffBypassTxDone, @@ -328,7 +328,7 @@ begin rxoutclk_out(0) => rxOutClkGt, txoutclk_out(0) => txOutClkGt, -- unused rxpmaresetdone_out(0) => rxPmaResetDoneInt, - rxresetdone_out(0) => rxResetDone, + rxresetdone_out(0) => rxResetDoneInt, rxsyncdone_out(0) => rxSyncDone, txpmaresetdone_out(0) => txPmaResetDone, txresetdone_out(0) => txResetDone); @@ -440,14 +440,16 @@ begin txUsrActive <= txUsrClkActive and txPmaResetDone; rxUsrActive <= rxUsrClkActive and rxPmaResetDoneInt; - rxPmaResetDone <= rxPmaResetDoneInt; + rxPmaResetDone <= rxPmaResetDoneInt; + + rxResetDone <= rxResetDoneInt and buffBypassRxDone; + phyRxReady <= rxResetDoneInt; cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); rstSyncRxIn <= rxResetAlignCheck or rxReset; rxResetGt <= rxResetAlignCheck or rxReset; - txOutClk <= txOutClkB; rxOutClk <= rxOutClkB; diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index 0e909ac6e7..2a2acd11d8 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -114,24 +114,22 @@ architecture mapping of Pgp2fcGthUltra is begin pgpTxResetDone <= phyTxReady; - pgpRxResetDone <= phyRxReady; U_RstSync_1 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetGt, -- [in] clk => stableClk, -- [in] rstOut => resetGtSync); -- [out] - --gtHardReset <= resetGtSync or stableRst; - gtHardReset <= stableRst; + gtHardReset <= resetGtSync or stableRst; U_RstSync_4 : entity surf.SynchronizerOneShot generic map ( TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + PULSE_WIDTH_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( clk => stableClk, -- [in] dataIn => phyRxInit, -- [in] @@ -141,7 +139,7 @@ begin U_RstSync_2 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpRxIn.resetRx, -- [in] clk => stableClk, -- [in] @@ -152,7 +150,7 @@ begin U_RstSync_3 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetTx, -- [in] clk => stableClk, -- [in] @@ -177,6 +175,7 @@ begin phyTxReady => phyTxReady, pgpRxClk => pgpRxClk, pgpRxClkRst => pgpRxReset, + pgpRxPhyRst => gtRxUserReset, pgpRxIn => pgpRxIn, pgpRxOut => pgpRxOut, pgpRxMasters => pgpRxMasters, @@ -206,9 +205,10 @@ begin gtRxN => pgpGtRxN, gtTxP => pgpGtTxP, gtTxN => pgpGtTxN, + phyRxReady => phyRxReady, rxReset => gtRxUserReset, rxUsrClkActive => pgpRxMmcmLocked, - rxResetDone => phyRxReady, + rxResetDone => pgpRxResetDone, rxPmaResetDone => pgpRxPmaResetDone, rxUsrClk => pgpRxClk, rxData => phyRxLaneIn.data, From 96b2e72ab107d13145633fc07371844852a6fc5f Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 15:00:11 -0700 Subject: [PATCH 61/86] Rebuild DCPs --- protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp | 4 ++-- protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp index b486d6d0d4..4d0bb5b5ef 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ip/Pgp2fcGthCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c314b33708fd6066744d54a39e3a7b930064887035fa04e70461cff709764ea4 -size 268201 +oid sha256:6e46ae2eb23a233cbf69adcf67ae5ad33e207faae05f7efd66d5ce2bd46a7228 +size 269166 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp index f4d0713e61..0ade87312e 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:e01e8db42b516ac33055c747ad08519c9895d9df75b9d52b2a9872269b84d8f7 -size 269272 +oid sha256:ea0418924902dfa4a90daf4c37fe66177fecd86f1c6ab4234b3f3bb45ff2cfa9 +size 269345 From 1a2e862f9074768fd037649f9e64f376c0d55def Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 4 Oct 2024 16:30:58 -0700 Subject: [PATCH 62/86] shorter rst pulse duration --- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 3ba9cf74e7..9674d6a923 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -127,14 +127,13 @@ begin gtHardReset <= resetGtSync or stableRst; - U_RstSync_4 : entity surf.SynchronizerOneShot + U_RstSync_4 : entity surf.Synchronizer generic map ( - TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + TPD_G => TPD_G) port map ( - clk => stableClk, -- [in] - dataIn => phyRxInit, -- [in] - dataOut => phyRxInitSync); -- [out] + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => phyRxInitSync); -- [out] -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset U_RstSync_2 : entity surf.PwrUpRst From bf1331d5a2b1ea54606c991ef0aca08029646be4 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 8 Oct 2024 15:48:05 -0700 Subject: [PATCH 63/86] Shorter rx reset pulse for faster locking --- .../pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index 2a2acd11d8..807b8dd020 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -126,15 +126,14 @@ begin gtHardReset <= resetGtSync or stableRst; - U_RstSync_4 : entity surf.SynchronizerOneShot + U_RstSync_4 : entity surf.Synchronizer generic map ( - TPD_G => TPD_G, - PULSE_WIDTH_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + TPD_G => TPD_G) port map ( - clk => stableClk, -- [in] - dataIn => phyRxInit, -- [in] - dataOut => phyRxInitSync); -- [out] - + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => phyRxInitSync); -- [out] + -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset U_RstSync_2 : entity surf.PwrUpRst generic map ( From 27b58e08224ee17e581dc52d342874fb4cdeb5c3 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Wed, 9 Oct 2024 12:37:30 -0700 Subject: [PATCH 64/86] refine rst duration and remove OR of GT resets --- .../pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd | 4 ++-- .../pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd index 58acee6faf..92ec1bf5e1 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -447,8 +447,8 @@ begin cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); - rstSyncRxIn <= rxResetAlignCheck or rxReset; - rxResetGt <= rxResetAlignCheck or rxReset; + rstSyncRxIn <= rxResetAlignCheck; + rxResetGt <= rxResetAlignCheck; txOutClk <= txOutClkB; rxOutClk <= rxOutClkB; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd index 9674d6a923..18c4d93830 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -115,11 +115,11 @@ begin pgpTxResetDone <= phyTxReady; - -- assuming a 78.125MHz stableClk + -- assuming a 185.714/2 = 92.857 MHz stableClk U_RstSync_1 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetGt, -- [in] clk => stableClk, -- [in] @@ -139,7 +139,7 @@ begin U_RstSync_2 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpRxIn.resetRx, -- [in] clk => stableClk, -- [in] @@ -150,7 +150,7 @@ begin U_RstSync_3 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetTx, -- [in] clk => stableClk, -- [in] From 97153eec756801387a46193f63a15b1009068d12 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 11 Oct 2024 09:45:13 -0700 Subject: [PATCH 65/86] Add more significant digits to clock frequency displays --- python/surf/protocols/pgp/_Pgp2fcAxi.py | 4 ++-- python/surf/xilinx/_GtRxAlignCheck.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/python/surf/protocols/pgp/_Pgp2fcAxi.py b/python/surf/protocols/pgp/_Pgp2fcAxi.py index 17fdf54518..d5a0b9cc06 100644 --- a/python/surf/protocols/pgp/_Pgp2fcAxi.py +++ b/python/surf/protocols/pgp/_Pgp2fcAxi.py @@ -425,7 +425,7 @@ def convtMHz(var, read): name = "RxClkFreq", mode = "RO", units = "MHz", - disp = '{:0.2f}', + disp = '{:0.6f}', dependencies = [self.RxClkFreqRaw], linkedGet = convtMHz, )) @@ -434,7 +434,7 @@ def convtMHz(var, read): name = "TxClkFreq", mode = "RO", units = "MHz", - disp = '{:0.2f}', + disp = '{:0.6f}', dependencies = [self.TxClkFreqRaw], linkedGet = convtMHz, )) diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py index e835f98679..77cb9d1d10 100644 --- a/python/surf/xilinx/_GtRxAlignCheck.py +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -79,7 +79,7 @@ def __init__( self, mode = 'RO', dependencies = [self.TxClkFreqRaw], linkedGet = lambda read: self.TxClkFreqRaw.get(read=read) * 1.0e-6, - disp = '{:0.3f}', + disp = '{:0.6f}', )) self.add(pr.RemoteVariable( @@ -98,7 +98,7 @@ def __init__( self, mode = 'RO', dependencies = [self.RxClkFreqRaw], linkedGet = lambda read: self.RxClkFreqRaw.get(read=read) * 1.0e-6, - disp = '{:0.3f}', + disp = '{:0.6f}', )) self.add(pr.RemoteVariable( From 440eb482b68f8eb1ad0e42041b9f1fa7a2bdd31f Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 17:42:30 +0200 Subject: [PATCH 66/86] added RoCEv2 README --- ethernet/RoCEv2/README.md | 20 +- ethernet/RoCEv2/blue-rdma/LICENSE | 340 ++++++++++++++++++++++++++++++ 2 files changed, 359 insertions(+), 1 deletion(-) create mode 100644 ethernet/RoCEv2/blue-rdma/LICENSE diff --git a/ethernet/RoCEv2/README.md b/ethernet/RoCEv2/README.md index 33caaafa79..aa81f0590f 100644 --- a/ethernet/RoCEv2/README.md +++ b/ethernet/RoCEv2/README.md @@ -1 +1,19 @@ -@FilMarini: Please write up some text about how these modules were auto-generated from BlueRdma \ No newline at end of file +@FilMarini: Please write up some text about how these modules were auto-generated from BlueRdma + +# Hardware Implementation of RoCEv2 Engine +This folder contains files generated from Bluespec SystemVerilog (BSV) source code located in different repositories: [blue-rdma](https://github.com/datenlord/blue-rdma), [blue-crc](https://github.com/datenlord/blue-crc) + +## Description +The verilog files in the `blue-rdma` and `blue-crc` folders represent a hardware implementation of the RoCEv2 engine and a iCRC calculation engine, respectively. +These files have been generated from a modified version of the BSV sources. The forked repo with the modifed version can be found [here](https://github.com/FilMarini/blue-rdma) + +The modifications consists in: + +* **Receiving Path Removed**: The RoCEv2 engine's receiving path as well as support for RDMA-Read operations has been entirely removed. + +* **Resource Optimization**: By removing the receiving path, the core now consumes fewer hardware resources, allowing it to fit on smaller FPGAs. + +## License information +The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders. + +Please ensure compliance with both licenses when using or modifying these files. \ No newline at end of file diff --git a/ethernet/RoCEv2/blue-rdma/LICENSE b/ethernet/RoCEv2/blue-rdma/LICENSE new file mode 100644 index 0000000000..1f963da0d1 --- /dev/null +++ b/ethernet/RoCEv2/blue-rdma/LICENSE @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. + From 8d3f2d6518fda4b61e6a153425f14777dc33d0d8 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 17:48:29 +0200 Subject: [PATCH 67/86] fixed oversight --- ethernet/RoCEv2/README.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/ethernet/RoCEv2/README.md b/ethernet/RoCEv2/README.md index aa81f0590f..61813bbbaa 100644 --- a/ethernet/RoCEv2/README.md +++ b/ethernet/RoCEv2/README.md @@ -1,5 +1,3 @@ -@FilMarini: Please write up some text about how these modules were auto-generated from BlueRdma - # Hardware Implementation of RoCEv2 Engine This folder contains files generated from Bluespec SystemVerilog (BSV) source code located in different repositories: [blue-rdma](https://github.com/datenlord/blue-rdma), [blue-crc](https://github.com/datenlord/blue-crc) @@ -16,4 +14,4 @@ The modifications consists in: ## License information The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders. -Please ensure compliance with both licenses when using or modifying these files. \ No newline at end of file +Please ensure compliance with both licenses when using or modifying these files. From 57644ce406a07cca99dd64732c92d59a5b8ddfe6 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 17:52:33 +0200 Subject: [PATCH 68/86] add blue-lib license --- ethernet/RoCEv2/blue-lib/LICENSE.md | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 ethernet/RoCEv2/blue-lib/LICENSE.md diff --git a/ethernet/RoCEv2/blue-lib/LICENSE.md b/ethernet/RoCEv2/blue-lib/LICENSE.md new file mode 100644 index 0000000000..e762d7e3aa --- /dev/null +++ b/ethernet/RoCEv2/blue-lib/LICENSE.md @@ -0,0 +1,3 @@ +These files are taken from the [B-Lang-org/bsc](https://github.com/B-Lang-org/bsc) repo. + +The license file from the original repo applies to the files in this folder From 0a35dc8761eff8d876c28bc66465d8497a0395c2 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 17:53:35 +0200 Subject: [PATCH 69/86] changed name of license file --- ethernet/RoCEv2/blue-lib/LICENSE.md | 3 --- 1 file changed, 3 deletions(-) delete mode 100644 ethernet/RoCEv2/blue-lib/LICENSE.md diff --git a/ethernet/RoCEv2/blue-lib/LICENSE.md b/ethernet/RoCEv2/blue-lib/LICENSE.md deleted file mode 100644 index e762d7e3aa..0000000000 --- a/ethernet/RoCEv2/blue-lib/LICENSE.md +++ /dev/null @@ -1,3 +0,0 @@ -These files are taken from the [B-Lang-org/bsc](https://github.com/B-Lang-org/bsc) repo. - -The license file from the original repo applies to the files in this folder From 31599fb0ba1d66c116aba045d246cd5d48ba4e9c Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 17:53:50 +0200 Subject: [PATCH 70/86] changed name of license file --- ethernet/RoCEv2/blue-lib/README.md | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 ethernet/RoCEv2/blue-lib/README.md diff --git a/ethernet/RoCEv2/blue-lib/README.md b/ethernet/RoCEv2/blue-lib/README.md new file mode 100644 index 0000000000..e762d7e3aa --- /dev/null +++ b/ethernet/RoCEv2/blue-lib/README.md @@ -0,0 +1,3 @@ +These files are taken from the [B-Lang-org/bsc](https://github.com/B-Lang-org/bsc) repo. + +The license file from the original repo applies to the files in this folder From 54c89cbeccdce81fa010075e9ae5dedaa381d74b Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 15 Oct 2024 18:17:04 +0200 Subject: [PATCH 71/86] modified README --- ethernet/RoCEv2/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ethernet/RoCEv2/README.md b/ethernet/RoCEv2/README.md index 61813bbbaa..a6d40bdd3b 100644 --- a/ethernet/RoCEv2/README.md +++ b/ethernet/RoCEv2/README.md @@ -11,6 +11,8 @@ The modifications consists in: * **Resource Optimization**: By removing the receiving path, the core now consumes fewer hardware resources, allowing it to fit on smaller FPGAs. +* **Fixed settings**: the generated verilog has support for 1 PD, 1 QP, 2 CQ and 2 MR, in order to be as light as possible. To change these settings, the core needs to be re-generated from its original or modified repo + ## License information The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders. From 46c5b3435d119abb49c82a8d085399c1dd0f70b3 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 16 Oct 2024 14:31:12 -0700 Subject: [PATCH 72/86] Decrease SyncClkFreq refresh rate for more accurate output --- protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd index b195fc35cd..264c108f97 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd @@ -331,9 +331,9 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, - CLK_LOWER_LIMIT_G => 155.0E+6, - CLK_UPPER_LIMIT_G => 158.0E+6, + REFRESH_RATE_G => 1.0, + CLK_LOWER_LIMIT_G => 185.0E+6, + CLK_UPPER_LIMIT_G => 187.0E+6, CNT_WIDTH_G => 32) port map ( freqOut => rxStatusSync.rxClkFreq, @@ -446,9 +446,9 @@ begin generic map ( TPD_G => TPD_G, REF_CLK_FREQ_G => AXI_CLK_FREQ_G, - REFRESH_RATE_G => 100.0, - CLK_LOWER_LIMIT_G => 155.0E+6, - CLK_UPPER_LIMIT_G => 158.0E+6, + REFRESH_RATE_G => 1.0, + CLK_LOWER_LIMIT_G => 185.0E+6, + CLK_UPPER_LIMIT_G => 187.0E+6, CNT_WIDTH_G => 32) port map ( freqOut => txStatusSync.txClkFreq, From fa0bbbd98ccf6e62aad6201a145cd1e3c4b8b432 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 16 Oct 2024 14:31:33 -0700 Subject: [PATCH 73/86] Show more decimal places for clock frequency --- python/surf/xilinx/_GtRxAlignCheck.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py index 77cb9d1d10..d9bb32df62 100644 --- a/python/surf/xilinx/_GtRxAlignCheck.py +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -156,7 +156,7 @@ def __init__( self, mode = 'RO', dependencies = [self.RefClkFreqRaw], linkedGet = lambda read: self.RefClkFreqRaw.get(read=read) * 1.0e-6, - disp = '{:0.3f}', + disp = '{:0.6f}', )) self.add(pr.RemoteVariable( From a835d77dec57f3523ae7b167cb75a8eb168862f1 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Mon, 28 Oct 2024 12:35:28 -0700 Subject: [PATCH 74/86] Remove unnecessary things from polling --- python/surf/protocols/pgp/_Pgp2fcAxi.py | 1 - python/surf/xilinx/_GtRxAlignCheck.py | 2 -- 2 files changed, 3 deletions(-) diff --git a/python/surf/protocols/pgp/_Pgp2fcAxi.py b/python/surf/protocols/pgp/_Pgp2fcAxi.py index d5a0b9cc06..d9f1deae56 100644 --- a/python/surf/protocols/pgp/_Pgp2fcAxi.py +++ b/python/surf/protocols/pgp/_Pgp2fcAxi.py @@ -181,7 +181,6 @@ def __init__(self, mode = "RO", base = pr.UInt, description = "", - pollInterval = 1, )) countVars = [ diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py index d9bb32df62..c362565abd 100644 --- a/python/surf/xilinx/_GtRxAlignCheck.py +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -60,7 +60,6 @@ def __init__( self, bitSize = 7, bitOffset = 0, mode = "RO", - pollInterval = 1, )) self.add(pr.RemoteVariable( @@ -167,7 +166,6 @@ def __init__( self, valueStride = 8, numValues = 40, mode = "RO", - pollInterval = 1, hidden = False, )) From 45f03506c96b6b2a656de6c0a59a6d1a41a75556 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 29 Oct 2024 09:29:33 -0700 Subject: [PATCH 75/86] Make gth match gty --- .../pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd | 4 ++-- .../pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd index 4dd2d6b469..2426c04a87 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthCoreWrapper.vhd @@ -447,8 +447,8 @@ begin cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); - rstSyncRxIn <= rxResetAlignCheck or rxReset; - rxResetGt <= rxResetAlignCheck or rxReset; + rstSyncRxIn <= rxResetAlignCheck; + rxResetGt <= rxResetAlignCheck; txOutClk <= txOutClkB; rxOutClk <= rxOutClkB; diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd index 807b8dd020..bf8186b6f8 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd +++ b/protocols/pgp/pgp2fc/gthUltraScale+/rtl/Pgp2fcGthUltra.vhd @@ -115,10 +115,11 @@ begin pgpTxResetDone <= phyTxReady; + -- assuming a 185.714/2 = 92.857 MHz stableClk U_RstSync_1 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetGt, -- [in] clk => stableClk, -- [in] @@ -133,12 +134,12 @@ begin clk => stableClk, -- [in] dataIn => phyRxInit, -- [in] dataOut => phyRxInitSync); -- [out] - + -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset U_RstSync_2 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpRxIn.resetRx, -- [in] clk => stableClk, -- [in] @@ -149,7 +150,7 @@ begin U_RstSync_3 : entity surf.PwrUpRst generic map ( TPD_G => TPD_G, - DURATION_G => ite(SIMULATION_G, 7813, 78130000)) -- 100us in sim; 1s in silicon + DURATION_G => ite(SIMULATION_G, 9285, 92850000)) -- 100us in sim; 1s in silicon port map ( arst => pgpTxIn.resetTx, -- [in] clk => stableClk, -- [in] From 83370baacdc839c9f3259694491890277f18b428 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Fri, 1 Nov 2024 13:44:49 -0700 Subject: [PATCH 76/86] Fix AxiLiteRingBuffer rogue device --- python/surf/axi/_AxiLiteRingBuffer.py | 36 +++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/python/surf/axi/_AxiLiteRingBuffer.py b/python/surf/axi/_AxiLiteRingBuffer.py index 6192407d76..4bb3d19174 100644 --- a/python/surf/axi/_AxiLiteRingBuffer.py +++ b/python/surf/axi/_AxiLiteRingBuffer.py @@ -28,59 +28,59 @@ def __init__(self, datawidth=32, **kwargs): ############################## self.add(pr.RemoteVariable( - name = 'blen', + name = 'BufferLength', description = 'Length of ring buffer', offset = 0x00, bitSize = 20, bitOffset = 0x00, base = pr.UInt, - mode = 'RW' + mode = 'RO' )) - self.add(pr.RemoteVariable( - name = 'clear', + self.add(pr.RemoteCommand( + name = 'ClearBuffer', description = 'Clear buffer', - offset = 0x03, + offset = 0x00, bitSize = 1, - bitOffset = 0x06, - base = pr.UInt, - mode = 'RW', + bitOffset = 30, + function = pr.Command.toggle )) self.add(pr.RemoteVariable( - name = 'enable', + name = 'BufEn', description = 'Enable buffer', - offset = 0x03, + offset = 0x00, bitSize = 1, - bitOffset = 0x07, - base = pr.UInt, + bitOffset = 31, + base = pr.Bool, mode = 'RW', )) - self.addRemoteVariables( + self.add(pr.RemoteVariable( name = 'data', description = 'Buffer values', offset = 0x4, bitSize = 32, bitOffset = 0x00, + valueBits = 32, + valueStride = 32, base = pr.UInt, mode = 'RO', - number = 0x3ff, - stride = 4, + numValues = 0x3ff, hidden = True, - ) + )) @self.command() def Dump(): mask = (1< 512: len_ = 256 buff = [] for i in range(len_): - buff.append( self.data[i].get() & mask ) + buff.append( self.data.get(index=i) & mask ) fmt = '{:0%d'%(self._datawidth/4)+'x} ' for i in range(len_): From 2387a0de1362ed7a5175ed323498b81d130a76a1 Mon Sep 17 00:00:00 2001 From: Christos Bakalis Date: Fri, 8 Nov 2024 14:32:14 -0800 Subject: [PATCH 77/86] fix gth/gty sourcing for pgp2fc --- protocols/pgp/pgp2fc/ruckus.tcl | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/protocols/pgp/pgp2fc/ruckus.tcl b/protocols/pgp/pgp2fc/ruckus.tcl index a542b35935..2121d8a8d8 100644 --- a/protocols/pgp/pgp2fc/ruckus.tcl +++ b/protocols/pgp/pgp2fc/ruckus.tcl @@ -12,9 +12,7 @@ if { ${family} eq {artix7} } { loadRuckusTcl "$::DIR_PATH/gtp7" } -if { ${family} eq {kintexuplus} || - ${family} eq {zynquplus} || - ${family} eq {zynquplusRFSOC} } { +if { ${family} eq {kintexuplus} } { loadRuckusTcl "$::DIR_PATH/gthUltraScale+" loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" } @@ -23,3 +21,8 @@ if { ${family} eq {virtexuplus} || ${family} eq {virtexuplusHBM} } { loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" } + +if { ${family} eq {zynquplus} || + ${family} eq {zynquplusRFSOC} } { + loadRuckusTcl "$::DIR_PATH/gthUltraScale+" +} From 8cb35dbe508ca41f0de1fd8da94a5741aa38f757 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 19 Nov 2024 11:25:17 -0800 Subject: [PATCH 78/86] Rename and hide variable --- python/surf/xilinx/_GtRxAlignCheck.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py index c362565abd..79377167e1 100644 --- a/python/surf/xilinx/_GtRxAlignCheck.py +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -159,14 +159,14 @@ def __init__( self, )) self.add(pr.RemoteVariable( - name = "PhaseCount", + name = "PhaseHistRaw", description = "Timing frame phase", offset = 0x00, valueBits = 8, valueStride = 8, numValues = 40, mode = "RO", - hidden = False, + hidden = True, )) for i in range(40): @@ -175,5 +175,5 @@ def __init__( self, guiGroup='Hist', disp = '{:d}', mode = 'RO', - dependencies = [self.PhaseCount], - linkedGet = lambda read, x=i: self.PhaseCount.get(read=read, index=x))) + dependencies = [self.PhaseHistRaw], + linkedGet = lambda read, x=i: self.PhaseHistRaw.value(index=x))) From 41870b91886b3d0c47b591c822366a19a7593b86 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Tue, 3 Dec 2024 13:28:07 -0800 Subject: [PATCH 79/86] Add SACIv2 files First pass, not compiled yet --- .../saci/rtl/AxiLiteSaci2Coordinator.vhd | 270 ++++++++++++++++ protocols/saci/rtl/Saci2Coordinator.vhd | 288 ++++++++++++++++++ protocols/saci/rtl/Saci2Subordinate.vhd | 164 ++++++++++ .../rtl/Saci2SubordinateAxiLiteMaster.vhd | 160 ++++++++++ 4 files changed, 882 insertions(+) create mode 100644 protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd create mode 100644 protocols/saci/rtl/Saci2Coordinator.vhd create mode 100644 protocols/saci/rtl/Saci2Subordinate.vhd create mode 100644 protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd diff --git a/protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd b/protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd new file mode 100644 index 0000000000..d3fc423136 --- /dev/null +++ b/protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd @@ -0,0 +1,270 @@ +------------------------------------------------------------------------------- +-- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Lite bridge to SACI bus +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.Saci2CoordinatorPkg.all; + +entity AxiLiteSaci2Coordinator is + generic ( + TPD_G : time := 1 ns; + AXIL_CLK_PERIOD_G : real := 8.0e-9; -- In units of seconds + AXIL_TIMEOUT_G : real := 1.0E-3; -- In units of seconds + SACI_CLK_PERIOD_G : real := 1.0e-6; -- In units of seconds + SACI_CLK_FREERUN_G : boolean := false; + SACI_ADDR_BITS_G : integer range 2 to 30 := 24; + SACI_NUM_CHIPS_G : positive := 1; + SACI_RSP_BUSSED_G : boolean := false); + port ( + -- SACI interface + saciClk : out sl; + saciCmd : out sl; + saciSelL : out slv(SACI_NUM_CHIPS_G-1 downto 0); + saciRsp : in slv(ite(SACI_RSP_BUSSED_G, 0, SACI_NUM_CHIPS_G-1) downto 0); + -- Optional SACI bus arbitration + saciBusReq : out sl; + saciBusGr : in sl := '1'; + -- Optional ASIC Global Reset + asicRstL : in sl := '1'; + -- AXI-Lite Register Interface + axilClk : in sl; + axilRst : in sl; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType); +end AxiLiteSaci2Coordinator; + +architecture rtl of AxiLiteSaci2Coordinator is + + constant CHIP_BITS_C : integer := log2(SACI_NUM_CHIPS_G); + constant TIMEOUT_C : integer := integer(AXIL_TIMEOUT_G/AXIL_CLK_PERIOD_G)-1; + + type StateType is ( + IDLE_S, + SACI_REQ_S, + SACI_ACK_S); + + type RegType is record + state : StateType; + saciBusReq : sl; + saciRst : sl; + req : sl; + chip : slv(log2(SACI_NUM_CHIPS_G)-1 downto 0); + op : sl; + addr : slv(29 downto 0); + wrData : slv(31 downto 0); + timer : integer range 0 to TIMEOUT_C; + axilReadSlave : AxiLiteReadSlaveType; + axilWriteSlave : AxiLiteWriteSlaveType; + + end record RegType; + + constant REG_INIT_C : RegType := ( + state => IDLE_S, + saciBusReq => '0', + saciRst => '1', + req => '0', + chip => (others => '0'), + op => '0', + addr => (others => '0'), + wrData => (others => '0'), + timer => 0, + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal ack : sl; + signal fail : sl; + signal rdData : slv(31 downto 0); + + -- attribute dont_touch : string; + -- attribute dont_touch of r : signal is "true"; + +begin + + assert (AXIL_CLK_PERIOD_G < 1.0) + report "AXIL_CLK_PERIOD_G must be < 1.0 seconds" severity failure; + assert (AXIL_TIMEOUT_G < 1.0) + report "AXIL_TIMEOUT_G must be < 1.0 seconds" severity failure; + assert (SACI_CLK_PERIOD_G < 1.0) + report "SACI_CLK_PERIOD_G must be < 1.0 seconds" severity failure; + assert (AXIL_CLK_PERIOD_G < AXIL_TIMEOUT_G) + report "AXIL_CLK_PERIOD_G must be < AXIL_TIMEOUT_G" severity failure; + assert (AXIL_CLK_PERIOD_G < SACI_CLK_PERIOD_G) + report "AXIL_CLK_PERIOD_G must be < SACI_CLK_PERIOD_G" severity failure; + assert (SACI_CLK_PERIOD_G < AXIL_TIMEOUT_G) + report "SACI_CLK_PERIOD_G must be < AXIL_TIMEOUT_G" severity failure; + + U_Saci2Coordinator_1 : entity surf.Saci2Coordinator + generic map ( + TPD_G => TPD_G, + SYS_CLK_PERIOD_G => AXIL_CLK_PERIOD_G, + SACI_CLK_PERIOD_G => SACI_CLK_PERIOD_G, + SACI_CLK_FREERUN_G => SACI_CLK_FREERUN_G, + SACI_NUM_CHIPS_G => SACI_NUM_CHIPS_G, + SACI_RSP_BUSSED_G => SACI_RSP_BUSSED_G) + port map ( + sysClk => axilClk, -- [in] + sysRst => r.saciRst, -- [in] + asicRstL => asicRstL, -- [in] + req => r.req, -- [in] + ack => ack, -- [out] + fail => fail, -- [out] + chip => r.chip, -- [in] + op => r.op, -- [in] + addr => r.addr, -- [in] + wrData => r.wrData, -- [in] + rdData => rdData, -- [out] + saciClk => saciClk, -- [out] + saciSelL => saciSelL, -- [out] + saciCmd => saciCmd, -- [out] + saciRsp => saciRsp); -- [in] + + comb : process (ack, asicRstL, axilReadMaster, axilRst, axilWriteMaster, fail, r, rdData, saciBusGr) is + variable v : RegType; + variable axilStatus : AxiLiteStatusType; + variable resp : slv(1 downto 0); + begin + -- Latch the current value + v := r; + + -- Reset the strobing signals + resp := AXI_RESP_OK_C; + + -- Check the timer + if r.timer /= TIMEOUT_C then + -- Increment the counter + v.timer := r.timer + 1; + end if; + + -- Determine the transaction type + axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axilStatus); + + -- State Machine + case (r.state) is + ---------------------------------------------------------------------- + when IDLE_S => + -- Reset the timer + v.saciRst := '0'; + v.timer := 0; + v.saciBusReq := '0'; + if (saciBusGr = '1') and (asicRstL = '1') then + -- Check for a write request + if (axilStatus.writeEnable = '1') then + v.saciBusReq := '1'; + -- SACI Commands + v.req := '1'; + v.op := '1'; + v.chip := axilWriteMaster.awaddr(SACI_ADDR_BITS_G+CHIP_BITS_C-1 downto SACI_ADDR_BITS_G); + if (SACI_NUM_CHIPS_G = 1) then + v.chip := "0"; + end if; + v.addr(SACI_ADDR_BITS_G-1 downto 0) := axilWriteMaster.awaddr(SACI_ADDR_BITS_G+1 downto 2); + v.wrData := axilWriteMaster.wdata; + -- Next state + v.state := SACI_REQ_S; + -- Check for a read request + elsif (axilStatus.readEnable = '1') then + v.saciBusReq := '1'; + -- SACI Commands + v.req := '1'; + v.op := '0'; + v.chip := axilReadMaster.araddr(SACI_ADDR_BITS_G+CHIP_BITS_C-1 downto SACI_ADDR_BITS_G); + if (SACI_NUM_CHIPS_G = 1) then + v.chip := "0"; + end if; + v.addr := axilReadMaster.araddr(SACI_ADDR_BITS_G+1 downto 2); + v.wrData := (others => '0'); + -- Next state + v.state := SACI_REQ_S; + end if; + else + if (axilStatus.writeEnable = '1') then + axiSlaveWriteResponse(v.axilWriteSlave, AXI_RESP_SLVERR_C); + elsif (axilStatus.readEnable = '1') then + axiSlaveReadResponse(v.axilReadSlave, AXI_RESP_SLVERR_C); + end if; + end if; + ---------------------------------------------------------------------- + when SACI_REQ_S => + if (ack = '1' and fail = '1') or (r.timer = TIMEOUT_C) then + -- Set the error flags + resp := AXI_RESP_SLVERR_C; + v.req := '0'; + v.saciRst := '1'; + elsif (ack = '1') then + -- Reset the flag + v.req := '0'; + end if; + + + if (v.req = '0') then + -- Check for Write operation + if (r.op = '1') then + --- Send AXI-Lite response + axiSlaveWriteResponse(v.axilWriteSlave, resp); + else + -- Return the read data bus + v.axilReadSlave.rdata := rdData; + -- Send AXI-Lite Response + axiSlaveReadResponse(v.axilReadSlave, resp); + end if; + -- Next state + v.state := SACI_ACK_S; + end if; + ---------------------------------------------------------------------- + when SACI_ACK_S => + -- Check status of ACK flag + if (ack = '0') then + -- Next state + v.state := IDLE_S; + end if; + ---------------------------------------------------------------------- + end case; + + -- Synchronous Reset + if axilRst = '1' then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Outputs + axilReadSlave <= r.axilReadSlave; + axilWriteSlave <= r.axilWriteSlave; + saciBusReq <= r.saciBusReq; + + end process comb; + + seq : process (axilClk) is + begin + if rising_edge(axilClk) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/protocols/saci/rtl/Saci2Coordinator.vhd b/protocols/saci/rtl/Saci2Coordinator.vhd new file mode 100644 index 0000000000..95e8e6a929 --- /dev/null +++ b/protocols/saci/rtl/Saci2Coordinator.vhd @@ -0,0 +1,288 @@ +------------------------------------------------------------------------------- +-- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Coordinator module for SACIv2 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; + +entity Saci2Coordinator is + + generic ( + TPD_G : time := 1 ns; + SYS_CLK_PERIOD_G : real := 8.0e-9; + SACI_CLK_PERIOD_G : real := 1.0e-6; + SACI_CLK_FREERUN_G : boolean := false; + SACI_NUM_CHIPS_G : positive := 1; + SACI_RSP_BUSSED_G : boolean := false); + port ( + -- Clock and Reset + sysClk : in sl; + sysRst : in sl; + + -- Optional ASIC Global Reset + asicRstL : in sl := '1'; + + -- Request interface + req : in sl; + ack : out sl; + fail : out sl; + chip : in slv(log2(SACI_NUM_CHIPS_G)-1 downto 0); + op : in sl; + addr : in slv(29 downto 0); + wrData : in slv(31 downto 0); + rdData : out slv(31 downto 0); + + -- Serial interface + saciClk : out sl; + saciSelL : out slv(SACI_NUM_CHIPS_G-1 downto 0); + saciCmd : out sl; + saciRsp : in slv(ite(SACI_RSP_BUSSED_G, 0, SACI_NUM_CHIPS_G-1) downto 0)); + + +end entity Saci2Coordinator; + +architecture rtl of Saci2Coordinator is + + constant SACI_CLK_HALF_PERIOD_C : integer := integer(SACI_CLK_PERIOD_G / (2.0*SYS_CLK_PERIOD_G))-1; + constant SACI_CLK_COUNTER_SIZE_C : integer := log2(SACI_CLK_HALF_PERIOD_C); + + type StateType is (IDLE_S, TX_S, RX_START_S, RX_HEADER_S, RX_DATA_S, ACK_S); + + type RegType is record + state : StateType; + shiftReg : slv(63 downto 0); + shiftCount : slv(6 downto 0); + asicRstL : slv(31 downto 0); + + --Saci clk gen + clkCount : slv(SACI_CLK_COUNTER_SIZE_C downto 0); + saciClkRising : sl; + saciClkFalling : sl; + + -- System Outputs + ack : sl; + fail : sl; + rdData : slv(31 downto 0); + + -- SACI Outputs + saciClk : sl; + saciSelL : slv(SACI_NUM_CHIPS_G-1 downto 0); + saciCmd : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + state => IDLE_S, + shiftReg => (others => '0'), + shiftCount => (others => '0'), + asicRstL => (others => '1'), + clkCount => (others => '0'), + saciClkRising => '0', + saciClkFalling => '0', + ack => '0', + fail => '0', + rdData => (others => '0'), + saciClk => '0', + saciSelL => (others => '1'), + saciCmd => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal saciRspSync : slv(saciRsp'range); + +begin + + assert (SACI_CLK_HALF_PERIOD_C >= 2) report "SACI_CLK_PERIOD_G is too fast for SYS_CLK_PERIOD_G" severity failure; + + ------------------------------------------------------------------------------------------------- + -- Synchronize saciRsp to sysClk + ------------------------------------------------------------------------------------------------- + RSP_SYNC : for i in saciRsp'range generate + U_Synchronizer_1 : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G) + port map ( + clk => sysClk, -- [in] + rst => sysRst, -- [in] + dataIn => saciRsp(i), -- [in] + dataOut => saciRspSync(i)); -- [out] + end generate RSP_SYNC; + + ------------------------------------------------------------------------------------------------- + -- Main logic + ------------------------------------------------------------------------------------------------- + comb : process (addr, asicRstL, chip, op, r, req, saciRspSync, sysRst, wrData) is + variable v : RegType; + variable rspIndex : integer; + begin + v := r; + + -- Default values + v.ack := '0'; + rspIndex := ite(SACI_RSP_BUSSED_G, 0, conv_integer(chip)); + + -- Run the saciClk + v.clkCount := r.clkCount + 1; + if (r.clkCount = SACI_CLK_HALF_PERIOD_C) then + v.saciClk := not r.saciClk; + v.clkCount := (others => '0'); + v.asicRstL := r.asicRstL(30 downto 0) & '1'; + end if; + + -- Create saciClk edge strobes + v.saciClkRising := '0'; + v.saciClkFalling := '0'; + if (r.clkCount = SACI_CLK_HALF_PERIOD_C-1) then + if (r.saciClk = '0') then + v.saciClkRising := '1'; + end if; + if (r.saciClk = '1') then + v.saciClkFalling := '1'; + end if; + end if; + + -- Check for ASIC reset condition + if (asicRstL = '0') then + -- Reset the bus + v.asicRstL := (others => '0'); + end if; + + case (r.state) is + when IDLE_S => + v.fail := '0'; + v.shiftReg := (others => '0'); + v.shiftCount := (others => '0'); + v.saciSelL := (others => '1'); + -- Hold clock inactive while idle else there is a ASIC reset + if (not SACI_CLK_FREERUN_G) and (r.asicRstL(31)='1') then + v.saciClk := '0'; + v.clkCount := (others => '0'); + end if; + + -- Start new command on the falling edge of saciClk + -- If clock is not freerunning then start right away + if (req = '1' and r.saciClk = '0' and r.clkCount = 0) then + -- New command, load shift reg + v.shiftReg(63) := '1'; -- Start bit + v.shiftReg(62) := op; + v.shiftReg(61 downto 32) := addr; + if (op = '1') then + v.shiftReg(31 downto 0) := wrData; + else + v.shiftReg(31 downto 0) := (others => '0'); + end if; + -- Assert saciSelL line + v.saciSelL := not decode(chip)(SACI_NUM_CHIPS_G-1 downto 0); + v.state := TX_S; + end if; + + when TX_S => + -- Shift out data on rising edge of saciClk + if r.saciClkRising = '1' then + v.saciCmd := r.shiftReg(63); + v.shiftReg := r.shiftReg(62 downto 0) & '0'; + v.shiftCount := r.shiftCount + 1; + end if; + + if (op = '0' and r.shiftCount = 32) then -- Read + v.state := RX_START_S; + elsif (op = '1' and r.shiftCount = 64) then -- Write + v.state := RX_START_S; + end if; + + + when RX_START_S => + -- Clear last saciCmd on rising edge of saciCLk + if (r.saciClkRising = '1') then + v.saciCmd := '0'; + end if; + + -- Wait for saciRsp start bit + v.shiftCount := (others => '0'); + if (saciRspSync(rspIndex) = '1' and r.saciClkFalling = '1') then + v.state := RX_HEADER_S; + end if; + + when RX_HEADER_S => + -- Shift data in and check that header is correct + if (r.saciClkFalling = '1') then + v.shiftCount := r.shiftCount + 1; + v.shiftReg := r.shiftReg(r.shiftReg'high-1 downto r.shiftReg'low) & saciRspSync(rspIndex); + end if; + + if (r.shiftCount = 31) then + -- Check that op, cmd and addr in response are correct + if (r.shiftReg(30) /= op or + r.shiftReg(29 downto 0) /= addr) then + v.fail := '1'; + end if; + + if (op = '0') then + v.state := RX_DATA_S; + else + v.state := ACK_S; + end if; + end if; + + when RX_DATA_S => + if (r.saciClkFalling = '1') then + v.shiftCount := r.shiftCount + 1; + v.shiftReg := r.shiftReg(r.shiftReg'high-1 downto r.shiftReg'low) & saciRspSync(rspIndex); + if (r.shiftCount = 64) then + v.state := ACK_S; + end if; + end if; + + + when ACK_S => + v.ack := '1'; + v.rdData := r.shiftReg(31 downto 0); + if (req = '0') then + v.ack := '0'; + v.fail := '0'; + v.state := IDLE_S; + end if; + + end case; + + if (sysRst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + saciSelL <= r.saciSelL; + saciCmd <= r.saciCmd; + saciClk <= r.saciClk; + ack <= r.ack; + fail <= r.fail; + rdData <= r.rdData; + + end process comb; + + seq : process (sysClk) is + begin + if (rising_edge(sysClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + +end architecture rtl; diff --git a/protocols/saci/rtl/Saci2Subordinate.vhd b/protocols/saci/rtl/Saci2Subordinate.vhd new file mode 100644 index 0000000000..cb9ae98ebe --- /dev/null +++ b/protocols/saci/rtl/Saci2Subordinate.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Subordinate module for SACIv2 interface. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity Saci2Subordinate is + + generic ( + TPD_G : time := 1 ns); + + port ( + rstL : in sl; -- ASIC global reset + + -- Serial Interface + saciClk : in sl; + saciSelL : in sl; -- chipSelect + saciCmd : in sl; + saciRsp : out sl; + + -- Silly reset hack to get saciSelL | rst onto dedicated reset bar + rstOutL : out sl; + rstInL : in sl; + + -- Detector (Parallel) Interface + exec : out sl; + ack : in sl; + readL : out sl; + addr : out slv(29 downto 0); + wrData : out slv(31 downto 0); + rdData : in slv(31 downto 0)); + +end entity SaciSubordinate; + +architecture rtl of SaciSubordinate is + + type StateType is (WAIT_START_S, SHIFT_IN_S); + + type RegType is record + shiftReg : slv(65 downto 0); + state : StateType; + exec : sl; + readL : sl; + end record RegType; + + signal r, rin : RegType; + signal saciCmdFall : sl; + + procedure shiftInLeft ( + i : in sl; + v : inout slv) is + begin + v := v(v'high-1 downto v'low) & i; + end procedure shiftInLeft; + +begin + + -- Chip select also functions as async reset + rstOutL <= rstL and not saciSelL; + + + -- Clock in serial input on falling edge + fall : process (saciClk, rstInL) is + begin + if (rstInL = '0') then + saciCmdFall <= '0' after TPD_G; + elsif (falling_edge(saciClk)) then + saciCmdFall <= saciCmd after TPD_G; + end if; + end process fall; + + + seq : process (saciClk, rstInL) is + begin + if (rstInL = '0') then + r.shiftReg <= (others => '0') after TPD_G; + r.state <= WAIT_START_S after TPD_G; + r.exec <= '0' after TPD_G; + r.readL <= '0' after TPD_G; + elsif (rising_edge(saciClk)) then + r <= rin after TPD_G; + end if; + end process seq; + + comb : process (r, saciCmdFall, ack, rdData, saciSelL) is + variable v : RegType; + begin + v := r; + + shiftInLeft(saciCmdFall, v.shiftReg); + + -- Main state machine + case (r.state) is + + when WAIT_START_S => + + -- Shift data out and look for next start bit + if (r.shiftReg(0) = '1') then + v.state := SHIFT_IN_S; + end if; + + when SHIFT_IN_S => + -- Wait for start bit to shift all the way in then assert exec and readL + if (r.shiftReg(63) = '1') then + v.exec := '1'; + v.readL := r.shiftReg(62); + end if; + + if (r.exec = '1') then + v.shiftReg := r.shiftReg; -- Pause shifting when exec high + v.readL := r.readL; + end if; + + if (ack = '1') then + v.exec := '0'; + v.state := WAIT_START_S; + if (r.shiftReg(63) = '1') then + v.shiftReg(32 downto 1) := (others => '0'); -- write + else + v.shiftReg(32 downto 1) := rdData; -- read + end if; + end if; + + + when others => + v.shiftReg := (others => '0'); + v.state := WAIT_START_S; + v.exec := '0'; + v.readL := '0'; + + end case; + + + rin <= v; + + -- Assign outputs from registers + exec <= r.exec; + readL <= r.readL; + saciRsp <= r.shiftReg(65); + addr <= r.shiftReg(62 downto 33); + wrData <= r.shiftReg(32 downto 1); + + end process comb; + + +end architecture rtl; + diff --git a/protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd b/protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd new file mode 100644 index 0000000000..74e63a6b3f --- /dev/null +++ b/protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd @@ -0,0 +1,160 @@ +------------------------------------------------------------------------------- +-- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Lite master bridge for SACI bus slave +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.SaciMasterPkg.all; + +entity SaciAxiLiteMaster is + generic ( + TPD_G : time := 1 ns); + port ( + -- Global Reset + rstL : in sl; + -- SACI Slave interface + saciClk : in sl; + saciCmd : in sl; + saciSelL : in sl; + saciRsp : out sl; + -- AXI-Lite Register Interface + axilClk : in sl; + axilRst : in sl; + axilReadMaster : out AxiLiteReadMasterType; + axilReadSlave : in AxiLiteReadSlaveType; + axilWriteMaster : out AxiLiteWriteMasterType; + axilWriteSlave : in AxiLiteWriteSlaveType); +end SaciAxiLiteMaster; + +architecture rtl of SaciAxiLiteMaster is + + -- AXI-Lite Master Interface + signal axilReq : AxiLiteReqType; + signal axilAck : AxiLiteAckType; + + -- SACI resets + signal rstOutL : sl; + signal rstInL : sl; + + + -- SACI Slave parallel interface + signal exec : sl; + signal ack : sl; + signal readL : sl; + signal addr : slv(29 downto 0); + signal wrData : slv(31 downto 0); + signal rdData : slv(31 downto 0); + + + -- attribute dont_touch : string; + -- attribute dont_touch of r : signal is "true"; + +begin + + rstInL <= rstOutL; + + U_SaciSlave_1 : entity surf.Saci2Subordinate + generic map ( + TPD_G => TPD_G) + port map ( + rstL => rstL, -- [in] + saciClk => saciClk, -- [in] + saciSelL => saciSelL, -- [in] + saciCmd => saciCmd, -- [in] + saciRsp => saciRsp, -- [out] + rstOutL => rstOutL, -- [out] + rstInL => rstInL, -- [in] + exec => exec, -- [out] + ack => ack, -- [in] + readL => readL, -- [out] + cmd => cmd, -- [out] + addr => addr, -- [out] + wrData => wrData, -- [out] + rdData => rdData); -- [in] + + ------------------------------------------------------ + -- Synchronize exec to axilReq.request + ------------------------------------------------------ + U_Synchronizer_1 : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + OUT_POLARITY_G => '1', + RST_ASYNC_G => true, + STAGES_G => 2, + BYPASS_SYNC_G => false, + INIT_G => "0") + port map ( + clk => axilClk, -- [in] + rst => axilRst, -- [in] + dataIn => exec, -- [in] + dataOut => axilReq.request); -- [out] + + ------------------------------------------------------ + -- These should have settled to be sampled by axilClk + -- By the time exec gets synced to axilReq + ------------------------------------------------------ + axilReq.rnw <= not readL; + axilReq.address(1 downto 0) <= "00"; + axilReq.address(31 downto 2) <= addr; + axilReq.wrData <= wrData; + + ------------------------------------------------------ + -- Synchronize axilAck.done to saciClk + ------------------------------------------------------ + U_Synchronizer_2 : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + OUT_POLARITY_G => '1', + RST_ASYNC_G => true, + STAGES_G => 2, + BYPASS_SYNC_G => false, + INIT_G => "0") + port map ( + clk => saciClk, -- [in] + rst => '0', -- [in] + dataIn => axilAck.done, -- [in] + dataOut => ack); -- [out] + + ------------------------------------------------------ + -- This should have settled to be sampled by saciClk + -- By the time axilAck.done gets synced to ack + ------------------------------------------------------ + rdData <= axilAck.rdData; + + U_AxiLiteMaster_1 : entity surf.AxiLiteMaster + generic map ( + TPD_G => TPD_G, + RST_ASYNC_G => true) + port map ( + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + req => axilReq, -- [in] + ack => axilAck, -- [out] + axilWriteMaster => axilWriteMaster, -- [out] + axilWriteSlave => axilWriteSlave, -- [in] + axilReadMaster => axilReadMaster, -- [out] + axilReadSlave => axilReadSlave); -- [in] + + +end rtl; From c5a286ca522b89d4140024030fd8df88b3cb4fe5 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 3 Dec 2024 16:49:07 -0800 Subject: [PATCH 80/86] reorg of SACI version1 vs version 2 src code --- protocols/saci/ruckus.tcl | 10 ++++------ protocols/saci/{ => saci1}/doc/SACI.pptx | Bin protocols/saci/{ => saci1}/doc/SaciRdCmd.png | Bin protocols/saci/{ => saci1}/doc/SaciRdCmd.svg | 0 protocols/saci/{ => saci1}/doc/SaciRdRsp.png | Bin protocols/saci/{ => saci1}/doc/SaciRdRsp.svg | 0 protocols/saci/{ => saci1}/doc/SaciRead.tim | 0 protocols/saci/{ => saci1}/doc/SaciWrCmd-1.png | Bin protocols/saci/{ => saci1}/doc/SaciWrCmd.png | Bin protocols/saci/{ => saci1}/doc/SaciWrCmd.svg | 0 protocols/saci/{ => saci1}/doc/SaciWrRsp-1.png | Bin protocols/saci/{ => saci1}/doc/SaciWrRsp.png | Bin protocols/saci/{ => saci1}/doc/SaciWrRsp.svg | 0 protocols/saci/{ => saci1}/doc/SaciWrRsp1.png | Bin protocols/saci/{ => saci1}/doc/SaciWrRsp1.svg | 0 protocols/saci/{ => saci1}/doc/SaciWrite.tim | 0 protocols/saci/{ => saci1}/doc/Snap_Saci_rev2b.bmp | Bin protocols/saci/{ => saci1}/doc/waveforms.js | 0 .../saci/{ => saci1}/rtl/AxiLiteSaciMaster.vhd | 0 .../saci/{ => saci1}/rtl/SaciAxiLiteMaster.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciMaster.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciMaster2.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciMasterPkg.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciMasterSync.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciMultiPixel.vhd | 0 .../saci/{ => saci1}/rtl/SaciMultiPixelPkg.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciPrepRdout.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciSlave.vhd | 0 protocols/saci/{ => saci1}/rtl/SaciSlaveOld.vhd | 0 protocols/saci/saci1/ruckus.tcl | 8 ++++++++ .../saci/{ => saci1}/sim/AxiLiteSaciMasterTb.vhd | 0 protocols/saci/{ => saci1}/sim/FrontEndSaciPkg.vhd | 0 .../saci/{ => saci1}/sim/SaciAxiLiteMasterTb.vhd | 0 .../{ => saci1}/sim/SaciAxiLiteMasterTbWrapper.vhd | 0 protocols/saci/{ => saci1}/sim/SaciSlaveAnalog.v | 0 protocols/saci/{ => saci1}/sim/SaciSlaveRam.vhd | 0 protocols/saci/{ => saci1}/sim/SaciSlaveWrapper.vhd | 0 .../{ => saci2}/rtl/AxiLiteSaci2Coordinator.vhd | 0 protocols/saci/{ => saci2}/rtl/Saci2Coordinator.vhd | 0 protocols/saci/{ => saci2}/rtl/Saci2Subordinate.vhd | 0 .../rtl/Saci2SubordinateAxiLiteMaster.vhd | 0 protocols/saci/saci2/ruckus.tcl | 8 ++++++++ 42 files changed, 20 insertions(+), 6 deletions(-) rename protocols/saci/{ => saci1}/doc/SACI.pptx (100%) rename protocols/saci/{ => saci1}/doc/SaciRdCmd.png (100%) rename protocols/saci/{ => saci1}/doc/SaciRdCmd.svg (100%) rename protocols/saci/{ => saci1}/doc/SaciRdRsp.png (100%) rename protocols/saci/{ => saci1}/doc/SaciRdRsp.svg (100%) rename protocols/saci/{ => saci1}/doc/SaciRead.tim (100%) rename protocols/saci/{ => saci1}/doc/SaciWrCmd-1.png (100%) rename protocols/saci/{ => saci1}/doc/SaciWrCmd.png (100%) rename protocols/saci/{ => saci1}/doc/SaciWrCmd.svg (100%) rename protocols/saci/{ => saci1}/doc/SaciWrRsp-1.png (100%) rename protocols/saci/{ => saci1}/doc/SaciWrRsp.png (100%) rename protocols/saci/{ => saci1}/doc/SaciWrRsp.svg (100%) rename protocols/saci/{ => saci1}/doc/SaciWrRsp1.png (100%) rename protocols/saci/{ => saci1}/doc/SaciWrRsp1.svg (100%) rename protocols/saci/{ => saci1}/doc/SaciWrite.tim (100%) rename protocols/saci/{ => saci1}/doc/Snap_Saci_rev2b.bmp (100%) rename protocols/saci/{ => saci1}/doc/waveforms.js (100%) rename protocols/saci/{ => saci1}/rtl/AxiLiteSaciMaster.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciAxiLiteMaster.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMaster.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMaster2.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMasterPkg.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMasterSync.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMultiPixel.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciMultiPixelPkg.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciPrepRdout.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciSlave.vhd (100%) rename protocols/saci/{ => saci1}/rtl/SaciSlaveOld.vhd (100%) create mode 100644 protocols/saci/saci1/ruckus.tcl rename protocols/saci/{ => saci1}/sim/AxiLiteSaciMasterTb.vhd (100%) rename protocols/saci/{ => saci1}/sim/FrontEndSaciPkg.vhd (100%) rename protocols/saci/{ => saci1}/sim/SaciAxiLiteMasterTb.vhd (100%) rename protocols/saci/{ => saci1}/sim/SaciAxiLiteMasterTbWrapper.vhd (100%) rename protocols/saci/{ => saci1}/sim/SaciSlaveAnalog.v (100%) rename protocols/saci/{ => saci1}/sim/SaciSlaveRam.vhd (100%) rename protocols/saci/{ => saci1}/sim/SaciSlaveWrapper.vhd (100%) rename protocols/saci/{ => saci2}/rtl/AxiLiteSaci2Coordinator.vhd (100%) rename protocols/saci/{ => saci2}/rtl/Saci2Coordinator.vhd (100%) rename protocols/saci/{ => saci2}/rtl/Saci2Subordinate.vhd (100%) rename protocols/saci/{ => saci2}/rtl/Saci2SubordinateAxiLiteMaster.vhd (100%) create mode 100644 protocols/saci/saci2/ruckus.tcl diff --git a/protocols/saci/ruckus.tcl b/protocols/saci/ruckus.tcl index 42bed80299..06db36968f 100644 --- a/protocols/saci/ruckus.tcl +++ b/protocols/saci/ruckus.tcl @@ -1,8 +1,6 @@ -# Load RUCKUS library +# Load RUCKUS environment and library source $::env(RUCKUS_PROC_TCL) -# Load Source Code -loadSource -lib surf -dir "$::DIR_PATH/rtl" - -# Load Simulation -loadSource -lib surf -sim_only -dir "$::DIR_PATH/sim" +# Load ruckus files +loadRuckusTcl "$::DIR_PATH/saci1" +loadRuckusTcl "$::DIR_PATH/saci2" diff --git a/protocols/saci/doc/SACI.pptx b/protocols/saci/saci1/doc/SACI.pptx similarity index 100% rename from protocols/saci/doc/SACI.pptx rename to protocols/saci/saci1/doc/SACI.pptx diff --git a/protocols/saci/doc/SaciRdCmd.png b/protocols/saci/saci1/doc/SaciRdCmd.png similarity index 100% rename from protocols/saci/doc/SaciRdCmd.png rename to protocols/saci/saci1/doc/SaciRdCmd.png diff --git a/protocols/saci/doc/SaciRdCmd.svg b/protocols/saci/saci1/doc/SaciRdCmd.svg similarity index 100% rename from protocols/saci/doc/SaciRdCmd.svg rename to protocols/saci/saci1/doc/SaciRdCmd.svg diff --git a/protocols/saci/doc/SaciRdRsp.png b/protocols/saci/saci1/doc/SaciRdRsp.png similarity index 100% rename from protocols/saci/doc/SaciRdRsp.png rename to protocols/saci/saci1/doc/SaciRdRsp.png diff --git a/protocols/saci/doc/SaciRdRsp.svg b/protocols/saci/saci1/doc/SaciRdRsp.svg similarity index 100% rename from protocols/saci/doc/SaciRdRsp.svg rename to protocols/saci/saci1/doc/SaciRdRsp.svg diff --git a/protocols/saci/doc/SaciRead.tim b/protocols/saci/saci1/doc/SaciRead.tim similarity index 100% rename from protocols/saci/doc/SaciRead.tim rename to protocols/saci/saci1/doc/SaciRead.tim diff --git a/protocols/saci/doc/SaciWrCmd-1.png b/protocols/saci/saci1/doc/SaciWrCmd-1.png similarity index 100% rename from protocols/saci/doc/SaciWrCmd-1.png rename to protocols/saci/saci1/doc/SaciWrCmd-1.png diff --git a/protocols/saci/doc/SaciWrCmd.png b/protocols/saci/saci1/doc/SaciWrCmd.png similarity index 100% rename from protocols/saci/doc/SaciWrCmd.png rename to protocols/saci/saci1/doc/SaciWrCmd.png diff --git a/protocols/saci/doc/SaciWrCmd.svg b/protocols/saci/saci1/doc/SaciWrCmd.svg similarity index 100% rename from protocols/saci/doc/SaciWrCmd.svg rename to protocols/saci/saci1/doc/SaciWrCmd.svg diff --git a/protocols/saci/doc/SaciWrRsp-1.png b/protocols/saci/saci1/doc/SaciWrRsp-1.png similarity index 100% rename from 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similarity index 100% rename from protocols/saci/doc/SaciWrite.tim rename to protocols/saci/saci1/doc/SaciWrite.tim diff --git a/protocols/saci/doc/Snap_Saci_rev2b.bmp b/protocols/saci/saci1/doc/Snap_Saci_rev2b.bmp similarity index 100% rename from protocols/saci/doc/Snap_Saci_rev2b.bmp rename to protocols/saci/saci1/doc/Snap_Saci_rev2b.bmp diff --git a/protocols/saci/doc/waveforms.js b/protocols/saci/saci1/doc/waveforms.js similarity index 100% rename from protocols/saci/doc/waveforms.js rename to protocols/saci/saci1/doc/waveforms.js diff --git a/protocols/saci/rtl/AxiLiteSaciMaster.vhd b/protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd similarity index 100% rename from protocols/saci/rtl/AxiLiteSaciMaster.vhd rename to protocols/saci/saci1/rtl/AxiLiteSaciMaster.vhd diff --git a/protocols/saci/rtl/SaciAxiLiteMaster.vhd b/protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd similarity index 100% rename from protocols/saci/rtl/SaciAxiLiteMaster.vhd rename to protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd diff --git a/protocols/saci/rtl/SaciMaster.vhd b/protocols/saci/saci1/rtl/SaciMaster.vhd similarity index 100% rename from protocols/saci/rtl/SaciMaster.vhd rename to protocols/saci/saci1/rtl/SaciMaster.vhd diff --git a/protocols/saci/rtl/SaciMaster2.vhd b/protocols/saci/saci1/rtl/SaciMaster2.vhd similarity index 100% rename from protocols/saci/rtl/SaciMaster2.vhd rename to protocols/saci/saci1/rtl/SaciMaster2.vhd diff --git a/protocols/saci/rtl/SaciMasterPkg.vhd b/protocols/saci/saci1/rtl/SaciMasterPkg.vhd similarity index 100% rename from protocols/saci/rtl/SaciMasterPkg.vhd rename to protocols/saci/saci1/rtl/SaciMasterPkg.vhd diff --git a/protocols/saci/rtl/SaciMasterSync.vhd b/protocols/saci/saci1/rtl/SaciMasterSync.vhd similarity index 100% rename from protocols/saci/rtl/SaciMasterSync.vhd rename to protocols/saci/saci1/rtl/SaciMasterSync.vhd diff --git a/protocols/saci/rtl/SaciMultiPixel.vhd b/protocols/saci/saci1/rtl/SaciMultiPixel.vhd similarity index 100% rename from protocols/saci/rtl/SaciMultiPixel.vhd rename to protocols/saci/saci1/rtl/SaciMultiPixel.vhd diff --git a/protocols/saci/rtl/SaciMultiPixelPkg.vhd b/protocols/saci/saci1/rtl/SaciMultiPixelPkg.vhd similarity index 100% rename from protocols/saci/rtl/SaciMultiPixelPkg.vhd rename to protocols/saci/saci1/rtl/SaciMultiPixelPkg.vhd diff --git a/protocols/saci/rtl/SaciPrepRdout.vhd b/protocols/saci/saci1/rtl/SaciPrepRdout.vhd similarity index 100% rename from protocols/saci/rtl/SaciPrepRdout.vhd rename to protocols/saci/saci1/rtl/SaciPrepRdout.vhd diff --git a/protocols/saci/rtl/SaciSlave.vhd b/protocols/saci/saci1/rtl/SaciSlave.vhd similarity index 100% rename from protocols/saci/rtl/SaciSlave.vhd rename to protocols/saci/saci1/rtl/SaciSlave.vhd diff --git a/protocols/saci/rtl/SaciSlaveOld.vhd b/protocols/saci/saci1/rtl/SaciSlaveOld.vhd similarity index 100% rename from protocols/saci/rtl/SaciSlaveOld.vhd rename to protocols/saci/saci1/rtl/SaciSlaveOld.vhd diff --git a/protocols/saci/saci1/ruckus.tcl b/protocols/saci/saci1/ruckus.tcl new file mode 100644 index 0000000000..42bed80299 --- /dev/null +++ b/protocols/saci/saci1/ruckus.tcl @@ -0,0 +1,8 @@ +# Load RUCKUS library +source $::env(RUCKUS_PROC_TCL) + +# Load Source Code +loadSource -lib surf -dir "$::DIR_PATH/rtl" + +# Load Simulation +loadSource -lib surf -sim_only -dir "$::DIR_PATH/sim" diff --git a/protocols/saci/sim/AxiLiteSaciMasterTb.vhd b/protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd similarity index 100% rename from protocols/saci/sim/AxiLiteSaciMasterTb.vhd rename to protocols/saci/saci1/sim/AxiLiteSaciMasterTb.vhd diff --git a/protocols/saci/sim/FrontEndSaciPkg.vhd b/protocols/saci/saci1/sim/FrontEndSaciPkg.vhd similarity index 100% rename from protocols/saci/sim/FrontEndSaciPkg.vhd rename to protocols/saci/saci1/sim/FrontEndSaciPkg.vhd diff --git a/protocols/saci/sim/SaciAxiLiteMasterTb.vhd b/protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd similarity index 100% rename from protocols/saci/sim/SaciAxiLiteMasterTb.vhd rename to protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd diff --git a/protocols/saci/sim/SaciAxiLiteMasterTbWrapper.vhd b/protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd similarity index 100% rename from protocols/saci/sim/SaciAxiLiteMasterTbWrapper.vhd rename to protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd diff --git a/protocols/saci/sim/SaciSlaveAnalog.v b/protocols/saci/saci1/sim/SaciSlaveAnalog.v similarity index 100% rename from protocols/saci/sim/SaciSlaveAnalog.v rename to protocols/saci/saci1/sim/SaciSlaveAnalog.v diff --git a/protocols/saci/sim/SaciSlaveRam.vhd b/protocols/saci/saci1/sim/SaciSlaveRam.vhd similarity index 100% rename from protocols/saci/sim/SaciSlaveRam.vhd rename to protocols/saci/saci1/sim/SaciSlaveRam.vhd diff --git a/protocols/saci/sim/SaciSlaveWrapper.vhd b/protocols/saci/saci1/sim/SaciSlaveWrapper.vhd similarity index 100% rename from protocols/saci/sim/SaciSlaveWrapper.vhd rename to protocols/saci/saci1/sim/SaciSlaveWrapper.vhd diff --git a/protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd b/protocols/saci/saci2/rtl/AxiLiteSaci2Coordinator.vhd similarity index 100% rename from protocols/saci/rtl/AxiLiteSaci2Coordinator.vhd rename to protocols/saci/saci2/rtl/AxiLiteSaci2Coordinator.vhd diff --git a/protocols/saci/rtl/Saci2Coordinator.vhd b/protocols/saci/saci2/rtl/Saci2Coordinator.vhd similarity index 100% rename from protocols/saci/rtl/Saci2Coordinator.vhd rename to protocols/saci/saci2/rtl/Saci2Coordinator.vhd diff --git a/protocols/saci/rtl/Saci2Subordinate.vhd b/protocols/saci/saci2/rtl/Saci2Subordinate.vhd similarity index 100% rename from protocols/saci/rtl/Saci2Subordinate.vhd rename to protocols/saci/saci2/rtl/Saci2Subordinate.vhd diff --git a/protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd b/protocols/saci/saci2/rtl/Saci2SubordinateAxiLiteMaster.vhd similarity index 100% rename from protocols/saci/rtl/Saci2SubordinateAxiLiteMaster.vhd rename to protocols/saci/saci2/rtl/Saci2SubordinateAxiLiteMaster.vhd diff --git a/protocols/saci/saci2/ruckus.tcl b/protocols/saci/saci2/ruckus.tcl new file mode 100644 index 0000000000..4b81c406d0 --- /dev/null +++ b/protocols/saci/saci2/ruckus.tcl @@ -0,0 +1,8 @@ +# Load RUCKUS library +source $::env(RUCKUS_PROC_TCL) + +# Load Source Code +loadSource -lib surf -dir "$::DIR_PATH/rtl" + +# Load Simulation +#loadSource -lib surf -sim_only -dir "$::DIR_PATH/sim" From 16494f5710e970a5496882bfe8fdc13864484d6b Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 3 Dec 2024 17:14:55 -0800 Subject: [PATCH 81/86] code polishing --- ...aci2Coordinator.vhd => AxiLiteToSaci2.vhd} | 20 ++++++------- protocols/saci/saci2/rtl/Saci2Coordinator.vhd | 2 +- protocols/saci/saci2/rtl/Saci2Subordinate.vhd | 2 +- ...teAxiLiteMaster.vhd => Saci2ToAxiLite.vhd} | 28 +++++++------------ 4 files changed, 21 insertions(+), 31 deletions(-) rename protocols/saci/saci2/rtl/{AxiLiteSaci2Coordinator.vhd => AxiLiteToSaci2.vhd} (95%) mode change 100644 => 100755 rename protocols/saci/saci2/rtl/{Saci2SubordinateAxiLiteMaster.vhd => Saci2ToAxiLite.vhd} (90%) mode change 100644 => 100755 diff --git a/protocols/saci/saci2/rtl/AxiLiteSaci2Coordinator.vhd b/protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd old mode 100644 new mode 100755 similarity index 95% rename from protocols/saci/saci2/rtl/AxiLiteSaci2Coordinator.vhd rename to protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd index d3fc423136..bc9941d9f3 --- a/protocols/saci/saci2/rtl/AxiLiteSaci2Coordinator.vhd +++ b/protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +-- Title : SACI Version 2 Protocol: https://confluence.slac.stanford.edu/x/y3TDHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- @@ -19,13 +19,11 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -use surf.Saci2CoordinatorPkg.all; -entity AxiLiteSaci2Coordinator is +entity AxiLiteToSaci2 is generic ( TPD_G : time := 1 ns; AXIL_CLK_PERIOD_G : real := 8.0e-9; -- In units of seconds @@ -53,9 +51,9 @@ entity AxiLiteSaci2Coordinator is axilReadSlave : out AxiLiteReadSlaveType; axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType); -end AxiLiteSaci2Coordinator; +end AxiLiteToSaci2; -architecture rtl of AxiLiteSaci2Coordinator is +architecture rtl of AxiLiteToSaci2 is constant CHIP_BITS_C : integer := log2(SACI_NUM_CHIPS_G); constant TIMEOUT_C : integer := integer(AXIL_TIMEOUT_G/AXIL_CLK_PERIOD_G)-1; @@ -77,7 +75,6 @@ architecture rtl of AxiLiteSaci2Coordinator is timer : integer range 0 to TIMEOUT_C; axilReadSlave : AxiLiteReadSlaveType; axilWriteSlave : AxiLiteWriteSlaveType; - end record RegType; constant REG_INIT_C : RegType := ( @@ -143,7 +140,8 @@ begin saciCmd => saciCmd, -- [out] saciRsp => saciRsp); -- [in] - comb : process (ack, asicRstL, axilReadMaster, axilRst, axilWriteMaster, fail, r, rdData, saciBusGr) is + comb : process (ack, asicRstL, axilReadMaster, axilRst, axilWriteMaster, + fail, r, rdData, saciBusGr) is variable v : RegType; variable axilStatus : AxiLiteStatusType; variable resp : slv(1 downto 0); @@ -196,10 +194,10 @@ begin if (SACI_NUM_CHIPS_G = 1) then v.chip := "0"; end if; - v.addr := axilReadMaster.araddr(SACI_ADDR_BITS_G+1 downto 2); - v.wrData := (others => '0'); + v.addr(SACI_ADDR_BITS_G-1 downto 0) := axilReadMaster.araddr(SACI_ADDR_BITS_G+1 downto 2); + v.wrData := (others => '0'); -- Next state - v.state := SACI_REQ_S; + v.state := SACI_REQ_S; end if; else if (axilStatus.writeEnable = '1') then diff --git a/protocols/saci/saci2/rtl/Saci2Coordinator.vhd b/protocols/saci/saci2/rtl/Saci2Coordinator.vhd index 95e8e6a929..ae6d632597 100644 --- a/protocols/saci/saci2/rtl/Saci2Coordinator.vhd +++ b/protocols/saci/saci2/rtl/Saci2Coordinator.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +-- Title : SACI Version 2 Protocol: https://confluence.slac.stanford.edu/x/y3TDHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/saci/saci2/rtl/Saci2Subordinate.vhd b/protocols/saci/saci2/rtl/Saci2Subordinate.vhd index cb9ae98ebe..8db8a872cb 100644 --- a/protocols/saci/saci2/rtl/Saci2Subordinate.vhd +++ b/protocols/saci/saci2/rtl/Saci2Subordinate.vhd @@ -1,5 +1,5 @@ ------------------------------------------------------------------------------- --- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +-- Title : SACI Version 2 Protocol: https://confluence.slac.stanford.edu/x/y3TDHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- diff --git a/protocols/saci/saci2/rtl/Saci2SubordinateAxiLiteMaster.vhd b/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd old mode 100644 new mode 100755 similarity index 90% rename from protocols/saci/saci2/rtl/Saci2SubordinateAxiLiteMaster.vhd rename to protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd index 74e63a6b3f..9b8b1cc3e8 --- a/protocols/saci/saci2/rtl/Saci2SubordinateAxiLiteMaster.vhd +++ b/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd @@ -1,9 +1,9 @@ ------------------------------------------------------------------------------- --- Title : SACI Protocol: https://confluence.slac.stanford.edu/x/YYcRDQ +-- Title : SACI Version 2 Protocol: https://confluence.slac.stanford.edu/x/y3TDHw ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: AXI-Lite master bridge for SACI bus slave +-- Description: AXI-Lite master bridge for SACI Subordinate ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -19,13 +19,11 @@ use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; - library surf; use surf.StdRtlPkg.all; use surf.AxiLitePkg.all; -use surf.SaciMasterPkg.all; -entity SaciAxiLiteMaster is +entity Saci2ToAxiLite is generic ( TPD_G : time := 1 ns); port ( @@ -43,9 +41,9 @@ entity SaciAxiLiteMaster is axilReadSlave : in AxiLiteReadSlaveType; axilWriteMaster : out AxiLiteWriteMasterType; axilWriteSlave : in AxiLiteWriteSlaveType); -end SaciAxiLiteMaster; +end Saci2ToAxiLite; -architecture rtl of SaciAxiLiteMaster is +architecture mapping of Saci2ToAxiLite is -- AXI-Lite Master Interface signal axilReq : AxiLiteReqType; @@ -55,7 +53,6 @@ architecture rtl of SaciAxiLiteMaster is signal rstOutL : sl; signal rstInL : sl; - -- SACI Slave parallel interface signal exec : sl; signal ack : sl; @@ -64,10 +61,6 @@ architecture rtl of SaciAxiLiteMaster is signal wrData : slv(31 downto 0); signal rdData : slv(31 downto 0); - - -- attribute dont_touch : string; - -- attribute dont_touch of r : signal is "true"; - begin rstInL <= rstOutL; @@ -113,10 +106,10 @@ begin -- These should have settled to be sampled by axilClk -- By the time exec gets synced to axilReq ------------------------------------------------------ - axilReq.rnw <= not readL; - axilReq.address(1 downto 0) <= "00"; - axilReq.address(31 downto 2) <= addr; - axilReq.wrData <= wrData; + axilReq.rnw <= not readL; + axilReq.address(1 downto 0) <= "00"; + axilReq.address(31 downto 2) <= addr; + axilReq.wrData <= wrData; ------------------------------------------------------ -- Synchronize axilAck.done to saciClk @@ -156,5 +149,4 @@ begin axilReadMaster => axilReadMaster, -- [out] axilReadSlave => axilReadSlave); -- [in] - -end rtl; +end mapping; From e782aaea3c7625f1ff501d7efcaa8c15de33be03 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 3 Dec 2024 18:38:06 -0800 Subject: [PATCH 82/86] bug fix --- protocols/saci/saci2/rtl/Saci2Subordinate.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/saci/saci2/rtl/Saci2Subordinate.vhd b/protocols/saci/saci2/rtl/Saci2Subordinate.vhd index 8db8a872cb..4469c1c74e 100644 --- a/protocols/saci/saci2/rtl/Saci2Subordinate.vhd +++ b/protocols/saci/saci2/rtl/Saci2Subordinate.vhd @@ -47,9 +47,9 @@ entity Saci2Subordinate is wrData : out slv(31 downto 0); rdData : in slv(31 downto 0)); -end entity SaciSubordinate; +end entity Saci2Subordinate; -architecture rtl of SaciSubordinate is +architecture rtl of Saci2Subordinate is type StateType is (WAIT_START_S, SHIFT_IN_S); From c8e59142609c7283501f11f0b1a9bd49bf9caa83 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 3 Dec 2024 18:54:58 -0800 Subject: [PATCH 83/86] adding test_Saci2ToAxiLiteTb.py and bug fixes --- .../saci/saci1/sim/SaciAxiLiteMasterTb.vhd | 2 +- protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd | 1 - protocols/saci/saci2/ruckus.tcl | 2 +- protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd | 183 ++++++++++++++++++ tests/test_Saci2ToAxiLiteTb.py | 160 +++++++++++++++ 5 files changed, 345 insertions(+), 3 deletions(-) create mode 100755 protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd create mode 100755 tests/test_Saci2ToAxiLiteTb.py diff --git a/protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd b/protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd index 124e240027..3372461a3d 100644 --- a/protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd +++ b/protocols/saci/saci1/sim/SaciAxiLiteMasterTb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: surf.AxiLiteCrossbar cocoTB testbed +-- Description: surf.SaciAxiLiteMaster cocoTB testbed ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the diff --git a/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd b/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd index 9b8b1cc3e8..3e7a60b7a9 100755 --- a/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd +++ b/protocols/saci/saci2/rtl/Saci2ToAxiLite.vhd @@ -79,7 +79,6 @@ begin exec => exec, -- [out] ack => ack, -- [in] readL => readL, -- [out] - cmd => cmd, -- [out] addr => addr, -- [out] wrData => wrData, -- [out] rdData => rdData); -- [in] diff --git a/protocols/saci/saci2/ruckus.tcl b/protocols/saci/saci2/ruckus.tcl index 4b81c406d0..42bed80299 100644 --- a/protocols/saci/saci2/ruckus.tcl +++ b/protocols/saci/saci2/ruckus.tcl @@ -5,4 +5,4 @@ source $::env(RUCKUS_PROC_TCL) loadSource -lib surf -dir "$::DIR_PATH/rtl" # Load Simulation -#loadSource -lib surf -sim_only -dir "$::DIR_PATH/sim" +loadSource -lib surf -sim_only -dir "$::DIR_PATH/sim" diff --git a/protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd b/protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd new file mode 100755 index 0000000000..52c996d4b1 --- /dev/null +++ b/protocols/saci/saci2/sim/Saci2ToAxiLiteTb.vhd @@ -0,0 +1,183 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: surf.Saci2ToAxiLite cocoTB testbed +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity Saci2ToAxiLiteTb is + port ( + -- AXI-Lite Interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(31 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(31 downto 0); + S_AXI_WSTRB : in std_logic_vector(3 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(31 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(31 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic); +end Saci2ToAxiLiteTb; + +architecture mapping of Saci2ToAxiLiteTb is + + signal fpgaAxilClk : sl; + signal fpgaAxilRst : sl; + + signal fpgaAxilReadMaster : AxiLiteReadMasterType; + signal fpgaAxilReadSlave : AxiLiteReadSlaveType; + signal fpgaAxilWriteMaster : AxiLiteWriteMasterType; + signal fpgaAxilWriteSlave : AxiLiteWriteSlaveType; + + signal asicAxilClk : sl; + signal asicAxilRst : sl; + + signal asicAxilReadMaster : AxiLiteReadMasterType; + signal asicAxilReadSlave : AxiLiteReadSlaveType; + signal asicAxilWriteMaster : AxiLiteWriteMasterType; + signal asicAxilWriteSlave : AxiLiteWriteSlaveType; + + signal rstL : sl; + + signal saciClk : sl; + signal saciCmd : sl; + signal saciSelL : slv(0 downto 0); + signal saciRsp : slv(0 downto 0); + signal saciBusReq : sl; + signal saciBusGr : sl := '1'; + +begin + + U_ShimLayer : entity surf.SlaveAxiLiteIpIntegrator + generic map ( + EN_ERROR_RESP => true, + FREQ_HZ => 125000000, + ADDR_WIDTH => 32) + port map ( + -- IP Integrator AXI-Lite Interface + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWPROT => S_AXI_AWPROT, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARPROT => S_AXI_ARPROT, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_RREADY => S_AXI_RREADY, + -- SURF AXI-Lite Interface + axilClk => fpgaAxilClk, + axilRst => fpgaAxilRst, + axilReadMaster => fpgaAxilReadMaster, + axilReadSlave => fpgaAxilReadSlave, + axilWriteMaster => fpgaAxilWriteMaster, + axilWriteSlave => fpgaAxilWriteSlave); + + ------------------------------------------------------------------------------------------------- + -- FPGA Side + ------------------------------------------------------------------------------------------------- + U_AxiLiteToSaci2 : entity surf.AxiLiteToSaci2 + generic map ( + TPD_G => 1 ns, + AXIL_CLK_PERIOD_G => 8.0e-9, + AXIL_TIMEOUT_G => 1.0e-3, + SACI_CLK_PERIOD_G => 50.0e-9, + SACI_CLK_FREERUN_G => false, + SACI_NUM_CHIPS_G => 1, + SACI_RSP_BUSSED_G => false) + port map ( + saciClk => saciClk, -- [out] + saciCmd => saciCmd, -- [out] + saciSelL => saciSelL, -- [out] + saciRsp => saciRsp, -- [in] + saciBusReq => saciBusReq, -- [out] + saciBusGr => saciBusGr, -- [in] + axilClk => fpgaAxilClk, -- [in] + axilRst => fpgaAxilRst, -- [in] + axilReadMaster => fpgaAxilReadMaster, -- [in] + axilReadSlave => fpgaAxilReadSlave, -- [out] + axilWriteMaster => fpgaAxilWriteMaster, -- [in] + axilWriteSlave => fpgaAxilWriteSlave); -- [out] + + ------------------------------------------------------------------------------------------------- + -- ASIC side + ------------------------------------------------------------------------------------------------- + U_ClkRst_1 : entity surf.ClkRst + generic map ( + CLK_PERIOD_G => 8.0 ns) + port map ( + clkP => asicAxilClk, -- [out] + rst => asicAxilRst, -- [out] + rstL => rstL); -- [out] + + U_Saci2ToAxiLite : entity surf.Saci2ToAxiLite + generic map ( + TPD_G => 1 ns) + port map ( + rstL => rstL, -- [in] + saciClk => saciClk, -- [in] + saciCmd => saciCmd, -- [in] + saciSelL => saciSelL(0), -- [in] + saciRsp => saciRsp(0), -- [out] + axilClk => asicAxilClk, -- [in] + axilRst => asicAxilRst, -- [in] + axilReadMaster => asicAxilReadMaster, -- [in] + axilReadSlave => asicAxilReadSlave, -- [out] + axilWriteMaster => asicAxilWriteMaster, -- [in] + axilWriteSlave => asicAxilWriteSlave); -- [out] + + + U_MEM : entity surf.AxiDualPortRam + generic map ( + ADDR_WIDTH_G => 22, + DATA_WIDTH_G => 32) + port map ( + -- Axi Port + axiClk => asicAxilClk, + axiRst => asicAxilRst, + axiReadMaster => asicAxilReadMaster, + axiReadSlave => asicAxilReadSlave, + axiWriteMaster => asicAxilWriteMaster, + axiWriteSlave => asicAxilWriteSlave); + + +end mapping; diff --git a/tests/test_Saci2ToAxiLiteTb.py b/tests/test_Saci2ToAxiLiteTb.py new file mode 100755 index 0000000000..f776de276e --- /dev/null +++ b/tests/test_Saci2ToAxiLiteTb.py @@ -0,0 +1,160 @@ +############################################################################## +## This file is part of 'SLAC Firmware Standard Library'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'SLAC Firmware Standard Library', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiLiteBus, AxiLiteMaster + +# test_Saci2ToAxiLiteTb +from cocotb_test.simulator import run +import pytest +import glob +import os +import itertools +import logging + +class TB: + def __init__(self, dut): + + # Pointer to DUT object + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Start clock (125 MHz) in a separate thread + cocotb.start_soon(Clock(dut.S_AXI_ACLK, 8.0, units='ns').start()) + + # Create the AXI-Lite Master + self.axil_master = AxiLiteMaster( + bus = AxiLiteBus.from_prefix(dut, 'S_AXI'), + clock = dut.S_AXI_ACLK, + reset = dut.S_AXI_ARESETN, + reset_active_level=False) + + def set_idle_generator(self, generator=None): + if generator: + self.axil_master.write_if.aw_channel.set_pause_generator(generator()) + self.axil_master.write_if.w_channel.set_pause_generator(generator()) + self.axil_master.read_if.ar_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axil_master.write_if.b_channel.set_pause_generator(generator()) + self.axil_master.read_if.r_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.S_AXI_ARESETN.setimmediatevalue(0) + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 0 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + self.dut.S_AXI_ARESETN.value = 1 + await RisingEdge(self.dut.S_AXI_ACLK) + await RisingEdge(self.dut.S_AXI_ACLK) + + +async def run_test_words(dut): + + tb = TB(dut) + + await tb.cycle_reset() + + # Wait for internal reset to fall + await Timer(10, 'us') + + for offsetHigh in range(17): + for offsetLow in range(0, 0xF, 4): + high = 0 + if offsetHigh != 0: + high = (1 << (offsetHigh+3)) + addr = high | offsetLow + + test_data = addr.to_bytes(length=4, byteorder='little') + event = tb.axil_master.init_write(addr, test_data) + await event.wait() + event = tb.axil_master.init_read(addr, 4) + await event.wait() + assert event.data.data == test_data + + await RisingEdge(dut.S_AXI_ACLK) + await RisingEdge(dut.S_AXI_ACLK) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + ################# + # run_test_words + ################# + factory = TestFactory(run_test_words) + factory.generate_tests() + +tests_dir = os.path.dirname(__file__) +tests_module = 'Saci2ToAxiLiteTb' + +############################################################################## + +@pytest.mark.parametrize( + "parameters", [ + None + ]) +def test_Saci2ToAxiLiteTb(parameters): + + # https://github.com/themperek/cocotb-test#arguments-for-simulatorrun + # https://github.com/themperek/cocotb-test/blob/master/cocotb_test/simulator.py + run( + # top level HDL + toplevel = f'surf.{tests_module}'.lower(), + + # name of the file that contains @cocotb.test() -- this file + # https://docs.cocotb.org/en/stable/building.html?#envvar-MODULE + module = f'test_{tests_module}', + + # https://docs.cocotb.org/en/stable/building.html?#var-TOPLEVEL_LANG + toplevel_lang = 'vhdl', + + # VHDL source files to include. + # Can be specified as a list or as a dict of lists with the library name as key, + # if the simulator supports named libraries. + vhdl_sources = { + 'surf' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/surf/*'), + 'ruckus' : glob.glob(f'{tests_dir}/../build/SRC_VHDL/ruckus/*'), + }, + + # A dictionary of top-level parameters/generics. + parameters = parameters, + + # The directory used to compile the tests. (default: sim_build) + sim_build = f'{tests_dir}/sim_build/{tests_module}', + + # A dictionary of extra environment variables set in simulator process. + extra_env=parameters, + + # Select a simulator + simulator="ghdl", + + # use of synopsys package "std_logic_arith" needs the -fsynopsys option + # -frelaxed-rules option to allow IP integrator attributes + # When two operators are overloaded, give preference to the explicit declaration (-fexplicit) + vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'], + + ######################################################################## + # Dump waveform to file ($ gtkwave sim_build/path/To/{tests_module}.ghw) + ######################################################################## + # sim_args =[f'--wave={tests_module}.ghw'], + ) From ce86e6389f4e24d1249d0fe56218059cc066e9cc Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Tue, 3 Dec 2024 19:16:33 -0800 Subject: [PATCH 84/86] bug fix --- protocols/saci/saci2/rtl/Saci2Coordinator.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/protocols/saci/saci2/rtl/Saci2Coordinator.vhd b/protocols/saci/saci2/rtl/Saci2Coordinator.vhd index ae6d632597..2552f6b875 100644 --- a/protocols/saci/saci2/rtl/Saci2Coordinator.vhd +++ b/protocols/saci/saci2/rtl/Saci2Coordinator.vhd @@ -245,7 +245,7 @@ begin if (r.saciClkFalling = '1') then v.shiftCount := r.shiftCount + 1; v.shiftReg := r.shiftReg(r.shiftReg'high-1 downto r.shiftReg'low) & saciRspSync(rspIndex); - if (r.shiftCount = 64) then + if (r.shiftCount = 62) then v.state := ACK_S; end if; end if; From d452ae0ca232a9aa7f36622b9a9b12391acd2d09 Mon Sep 17 00:00:00 2001 From: Benjamin Reese Date: Wed, 4 Dec 2024 11:17:49 -0800 Subject: [PATCH 85/86] Add JSON for generating SACI2 waveforms in wavedrom --- protocols/saci/saci2/doc/SACIv2Waveforms.json | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 protocols/saci/saci2/doc/SACIv2Waveforms.json diff --git a/protocols/saci/saci2/doc/SACIv2Waveforms.json b/protocols/saci/saci2/doc/SACIv2Waveforms.json new file mode 100644 index 0000000000..96c56fce9a --- /dev/null +++ b/protocols/saci/saci2/doc/SACIv2Waveforms.json @@ -0,0 +1,28 @@ + +// This is for rendering waveforms with the wavedrom tool +// wavedrom.com/editor.html + +{signal: [['Coordinator', + {name: 'saciSelL', wave: '1.0......|.....|...|.......|..1.'}, + {name: 'saciClk', wave: 'p........|.....|...|.......|....'}, + {name: 'saciCmd', wave: '0..113...|.4...|.0.|.......|....', data: ['ADDR[31:2]', 'DATA[31:0]']}], + {},['Subordinate', + {name: 'saciRsp', wave: '=.0......|.....|...|.113...|.0=.', data: ['High-Z', 'ADDR[31:2]', 'HIGH-Z']}, +] +], + foot:{ + text:'SACIv2 Write', + } +} + +{signal: [['Coordinator', + {name: 'saciSelL', wave: '1.0......|..|........|.....|..1.'}, + {name: 'saciClk', wave: 'p........|..|........|.....|....'}, + {name: 'saciCmd', wave: '0..103...|.0|........|.....|....', data: ['ADDR[31:2]', ]}], + {},['Subordinate', + {name: 'saciRsp', wave: '=.0......|..|..103...|.4...|.0=.', data: ['High-Z', 'ADDR[31:2]', 'DATA[31:0]', 'HIGH-Z']}, +] +], + foot:{ + text:'SACIv2 Read', + }} From e3fbc5f02c77c28406b1d14b7d16ac9928619a4e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 5 Dec 2024 10:15:53 -0800 Subject: [PATCH 86/86] hot fix for ruckus.tcl --- protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl | 6 +++--- protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl index 2a46b90106..9b84c58b97 100644 --- a/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gthUltraScale+/ruckus.tcl @@ -2,7 +2,7 @@ source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_PROC_TCL) # Load local source Code and constraints -if { $::env(VIVADO_VERSION) >= 2020.1 } { +if { $::env(VIVADO_VERSION) >= 2024.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" @@ -11,11 +11,11 @@ if { $::env(VIVADO_VERSION) >= 2020.1 } { puts "Loading XCI file for PGP2FC" } else { loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" - } + } #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGthCore.dcp" #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGthCore.xci" } else { - puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2024.1 (or later)\n\n" } diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl index 3e72744e12..de793ba121 100644 --- a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl @@ -2,7 +2,7 @@ source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_PROC_TCL) # Load local source Code and constraints -if { $::env(VIVADO_VERSION) >= 2023.1 } { +if { $::env(VIVADO_VERSION) >= 2024.1 } { loadSource -lib surf -dir "$::DIR_PATH/rtl" @@ -11,10 +11,10 @@ if { $::env(VIVADO_VERSION) >= 2023.1 } { puts "Loading XCI file for PGP2FC" } else { loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" - } + } #loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" } else { - puts "\n\nWARNING: $::DIR_PATH requires Vivado 2023.1 (or later)\n\n" + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2024.1 (or later)\n\n" }