Bluetooth.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 17:45:05  November 28, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		Bluetooth_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY Bluetooth
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:05  NOVEMBER 28, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE src/uart_rx.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/helpers.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/clock_counter.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/bt.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/uart_tx.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
set_global_assignment -name QIP_FILE baud_gen.qip
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_A15 -to leds[0]
set_location_assignment PIN_L3 -to leds[7]
set_location_assignment PIN_B1 -to leds[6]
set_location_assignment PIN_F3 -to leds[5]
set_location_assignment PIN_D1 -to leds[4]
set_location_assignment PIN_A11 -to leds[3]
set_location_assignment PIN_B13 -to leds[2]
set_location_assignment PIN_A13 -to leds[1]
set_location_assignment PIN_R8 -to clk
set_location_assignment PIN_A2 -to tx
set_location_assignment PIN_E1 -to reset
set_location_assignment PIN_A3 -to rx
set_location_assignment PIN_J15 -to increment
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top