Module Name Overlap with Xilinx Internal

[christian-lanius]

Hi Everyone,
I am running a system made up in part of the modules provided in this repo and the AXI one. Additionally, I use some of the IP provided by Xilinx.
To simulate everything, I run vsim with all Xilinx libraries mapped. Unfortunately, some of the Xilinx internal modules share names with the modules in this repo, for example the "counter". In that case, simulation fails to start with errors like

# ** Fatal: (vsim-3350) Generic "<protected>" has not been given a value.
#    Time: 0 fs  Iteration: 0  Protected: /tb_sort_stage/mem_delay/i_axi_delayer/i_stream_delay_aw/gen_delay/<protected> File: {MYXILINXINSTALL}/data/ip/xilinx/cic_compiler_v4_0/hdl/cic_compiler_v4_0_vh_rfs.vhd Line: 73

The easy fix to this in my case is to rename the counter module to something unique. I wonder if/how this could be fixed in a more principled approach?

For completeness, here is my sim script:

vlog +incdir+../src/axi/include +incdir+../src/common_cells/include ../src/axi/src/*_pkg.sv
vlog +incdir+../src/axi/include +incdir+../src/common_cells/include ../src/common_cells/src/*_pkg.sv
vlog +incdir+../src/axi/include +incdir+../src/common_cells/include ../src/axi/src/*.sv
vlog +incdir+../src/axi/include +incdir+../src/common_cells/include ../src/common_cells/src/*.sv
#Own
vlog +incdir+.. ../tb/tb.sv
vlog +incdir+.. -cover bcst ../src/dut.sv

LIBS=""
# Xilinx Specific Stuff
for d in /eda/technology/xilinx/questa_lib/*/ ; do
	name=$(basename $d);
	vmap $name $d
	LIBS="$LIBS -L $name"
done
#vcom the xilinx ip simulation files here


#-coverage 
vsim $LIBS -voptargs="+acc" -suppress 3009 -debugDB work.tb