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    67 repositories

    • artlink

      Public
      A package for packaging, organizing, and combining artifacts
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Dec 2, 2024Dec 2, 2024

    • litex

      Public
      Build your hardware, easily!
      C
      •
      Other
      •573•0•0•0•Updated Nov 29, 2024Nov 29, 2024

    • litedram

      Public
      Small footprint and configurable DRAM core
      Python
      •
      Other
      •122•0•0•0•Updated Nov 29, 2024Nov 29, 2024

    • litejesd204b

      Public
      Small footprint and configurable JESD204B core
      Python
      •
      Other
      •12•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litesata

      Public
      Small footprint and configurable SATA core
      Python
      •
      Other
      •34•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litesdcard

      Public
      Small footprint and configurable SDCard core
      Python
      •
      Other
      •35•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •39•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • PYNQ

      Public
      Python Productivity for ZYNQ
      Jupyter Notebook
      •
      BSD 3-Clause "New" or "Revised" License
      •818•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • Surelog

      Public
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •68•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • liteiclink

      Public
      Small footprint and configurable Inter-Chip communication cores
      Python
      •
      Other
      •26•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • liteeth

      Public
      Small footprint and configurable Ethernet core
      Python
      •
      Other
      •87•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • hls4ml

      Public
      Machine learning on FPGAs using HLS
      C++
      •
      Apache License 2.0
      •420•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • verible

      Public
      Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
      C++
      •
      Other
      •214•1•0•0•Updated Oct 8, 2024Oct 8, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •617•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • prjxray

      Public
      Documenting the Xilinx 7-series bit-stream format.
      Python
      •
      ISC License
      •152•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • RapidWright

      Public
      Build Customized FPGA Implementations for Vivado
      Java
      •
      Other
      •109•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •894•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • UHDM

      Public
      Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
      C++
      •
      Apache License 2.0
      •40•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •520•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • amaranth-soc

      Public
      System on Chip toolkit for Amaranth HDL
      Python
      •
      BSD 2-Clause "Simplified" License
      •32•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • amaranth

      Public
      A modern hardware definition language and toolchain based on Python
      Python
      •
      BSD 2-Clause "Simplified" License
      •175•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • openFPGALoader

      Public
      Universal utility for programming FPGA
      C++
      •
      Apache License 2.0
      •264•1•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litex-boards

      Public
      LiteX boards files
      Python
      •
      BSD 2-Clause "Simplified" License
      •289•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litepcie

      Public
      Small footprint and configurable PCIe core
      Python
      •
      Other
      •119•1•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litespi

      Public
      Small footprint and configurable SPI core
      Python
      •
      BSD 2-Clause "Simplified" License
      •24•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • synlig

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •23•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • basejump_stl

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •99•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • litescope

      Public
      Small footprint and configurable embedded FPGA logic analyzer
      Python
      •
      Other
      •40•0•0•0•Updated Oct 8, 2024Oct 8, 2024

    • systemverilog-plugin

      Public
      SystemVerilog support for Yosys
      Verilog
      •
      Apache License 2.0
      •23•0•0•0•Updated Oct 8, 2024Oct 8, 2024