Requirements for test cases that will run in the cva6/verilator simulation environment?

[mtvaden]

Are there any notes/discussion regarding the requirements the
cva6/verilator simulation environment has for the test cases?

I am running cva6/verilator simulation using test cases
generated with the force-riscv ISG.
I have only observed a couple of requirements that the simulation environment
expects of each test case, but I suspect there are others that I have not identified.
Here are the requirements that I have identified so far:

1. Starting test case address 0x80000000.
2. End-of-test sequence requiring a write of a non-zero value
   to address 0x80001000 which has the symbol 'tohost' - apparently
   in a forever loop.

In the force-riscv tests, I am seeing assertion warnings where the
sd @ 0x360 in the debug module code is sometimes writing to an
address that causes a RESP_DECERR. I'm not seeing these assertions
pop when running the riscv-tests. I've not yet been able to determine
why that errant address is sometimes used.

[mtvaden]

It appears the cva6 platform is restricting the size of the DRAM to 1GB. The DRAM address range is then:

• starting address: 0x80000000
• ending address: 0xBFFFFFFF
  Constraining the addresses used in the tests to this range eliminates the RESP_DECERR warnings that I was getting.