Skip to content

Issues: llvm/circt

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

690 Open 1,425 Closed
690 Open 1,425 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

[MooreToCore] LSB and MSB support in moore dialect
#7925 opened Nov 29, 2024 by AndreyVV-100
[MooreToCore] moore.extract is converted to hw.array_slice when array's element type is also array
#7918 opened Nov 28, 2024 by slowlime
[FIRRTL] LowerLayers RefSend could be Canonicalized Away FIRRTL Involving the `firrtl` dialect
#7896 opened Nov 26, 2024 by seldridge
[FIRRTL] Can not canonicalize away memories without more care bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7880 opened Nov 22, 2024 by youngar
[HandshakeToDC] Tech debt: clk/rst inserted later than they probably should be HandshakeToDC
#7851 opened Nov 19, 2024 by teqdruid
[HandshakeToHW] Asserts with core dialects operations HandshakeToHW
#7850 opened Nov 19, 2024 by teqdruid
[FIRRTL] smem with read address from port does not work
#7834 opened Nov 19, 2024 by jackkoenig
1
[HandshakeToDC] Missing lowering for InstanceOp HandshakeToDC
#7828 opened Nov 15, 2024 by teqdruid
@mortbopet
[HandshakeToDC] Missing cf conversions and memory stuff HandshakeToDC
#7826 opened Nov 15, 2024 by teqdruid
@mortbopet
3
[Calyx] Floating Point Comparisons
#7821 opened Nov 15, 2024 by jiahanxie353
@jiahanxie353
7
[ImportVerilog] How to implement SVA in Moore? ImportVerilog
#7801 opened Nov 12, 2024 by chenbo-again
1
[FIRRTL] Remove backwards compatibility flag in Dedup FIRRTL Involving the `firrtl` dialect
#7800 opened Nov 12, 2024 by mikeurbach
[comb] Missing ~(~foo) canonicalization when foo is defined in another region
#7797 opened Nov 12, 2024 by rwy7
1
[SMT] How to go from Verilog to smtlib2 like with Yosys?
#7786 opened Nov 8, 2024 by flaviens
5
[FIRRTL] Parser Accepts Duplicated Names Under Layerblock bug Something isn't working FIRRTL Involving the `firrtl` dialect good first issue Good for newcomers
#7773 opened Nov 5, 2024 by seldridge
1
[Calyx] Copy attributes when creating new top level function
#7764 opened Nov 2, 2024 by jiahanxie353
@jiahanxie353
[circt-verilog] zero parameter at module declaration fails when used Moore
#7753 opened Oct 31, 2024 by dacsson
2
[Comb] i0 in concat is not folded
#7726 opened Oct 23, 2024 by uenoku
[LowerToHW] Failure when lowering bundle_create which contains zero bit
#7721 opened Oct 22, 2024 by uenoku
[ESI][Runtime][Cosim] Terminate with "pure virtual called" ESI
#7713 opened Oct 17, 2024 by teqdruid
[circt-lec] Report failing points enhancement New feature or request Logical Equivalence
#7711 opened Oct 17, 2024 by uenoku
1
[Verif] Add an optional name attribute to SymbolicValueOp
#7708 opened Oct 15, 2024 by uenoku
[Sim] Combine integer formatting ops into one op Simulator
#7692 opened Oct 10, 2024 by fabianschuiki
4
[FIRRTL] InferWidths: error can point at operation not involved in constraint bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7689 opened Oct 9, 2024 by youngar
[Calyx] IfOp's group has to be a CombGroupOp? Calyx The Calyx dialect
#7682 opened Oct 8, 2024 by jiahanxie353
3
ProTip! Find all open issues with in progress development work with linked:pr.