info.yaml

# Tiny Tapeout project information
project:
  title:        "SPI Test"
  author:       "Harald Pretl"
  discord:      "hpretl"
  description:  "Simple SPI-based register file (for the testing the flow)"
  language:     "Verilog"
  clock_hz:     20000000

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 6x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_hpretl_spi"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "tt_um_hpretl_spi.v"
    - "chain2.v"
    - "dsmod1.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "SPI clk (SCLK)"
  ui[1]: "SPI data in (MOSI)"
  ui[2]: "SPI load (CS)"
  ui[3]: "select output byte (0 = low, 1 = high)"
  ui[4]: "sinegen scale factor (LSB)"
  ui[5]: "sinegen scale factor (MSB)"
  ui[6]: "select ds-modulator input (0 = SPI register, 1 = sine generator)"
  ui[7]: "order of delta-sigma modulator (0 = 1st, 1 = 2nd)"

  # Outputs
  uo[0]: "SPI data out (MISO)"
  uo[1]: "cookie detected (loaded 0xCAFE)"
  uo[2]: "XOR of SPI clk and SPI data in"
  uo[3]: ""
  uo[4]: ""
  uo[5]: ""
  uo[6]: "inverted output of delta-sigma modulator"
  uo[7]: "output of delta-sigma modulator"

  # Bidirectional pins
  uio[0]: "register b0|8"
  uio[1]: "register b1|9"
  uio[2]: "register b2|10"
  uio[3]: "register b3|11"
  uio[4]: "register b4|12"
  uio[5]: "register b5|13"
  uio[6]: "register b6|14"
  uio[7]: "register b7|15"

# Do not change!
yaml_version: 6