(c) 2024 Harald Pretl, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria
This design implements a simple 8b input, 8b output freely programmable logic block with optional selectable feedback.
generated from TinyTapeout/ttihp-verilog-template
-
Notifications
You must be signed in to change notification settings - Fork 0
A simple 8b input, 8b output freely programmable logic block with optional selectable feedback.
License
iic-jku/ttihp-0p2-hpretl-minilogix
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
A simple 8b input, 8b output freely programmable logic block with optional selectable feedback.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published