Fix base_user_proj_example.sdc file for irq port constraints

[vijayank88]

As per RTL file

caravel_user_project/verilog/rtl/user_proj_example.v

Line 69 in ba57203

output [2:0] irq

the output port output [2:0] irq used at macro level.

But in sdc constraints it is used as user_irq

caravel_user_project/openlane/user_proj_example/base_user_proj_example.sdc

Line 126 in ba57203

set_output_delay -max 0.7 -clock [get_clocks {clk}] [get_ports {user_irq[*]}]

caravel_user_project/openlane/user_proj_example/base_user_proj_example.sdc

Line 131 in ba57203

set_output_delay -min 0 -clock [get_clocks {clk}] [get_ports {user_irq[*]}]

Facing following warnings during timing report.

Warning: base_user_proj_example.sdc line 126, port 'user_irq[*]' not found.
Warning: base_user_proj_example.sdc line 131, port 'user_irq[*]' not found.

Some of the user trying utilize irq port may lead to timing signoff issue.