From ab6692ef87f484008d5fa858d21646d5d4c5e9f4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ji=C5=99=C3=AD=20=C5=A0tefan?= <stefaji3@fel.cvut.cz>
Date: Sun, 25 Aug 2024 23:04:37 +0200
Subject: [PATCH] Fixed statistics for single-cycle core, fixed BHR UI not
 disabling properly

---
 src/gui/windows/predictor/predictor_info_dock.cpp |  7 ++++++-
 src/machine/core.cpp                              | 11 ++++++-----
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/gui/windows/predictor/predictor_info_dock.cpp b/src/gui/windows/predictor/predictor_info_dock.cpp
index 99965db6..35b1c716 100644
--- a/src/gui/windows/predictor/predictor_info_dock.cpp
+++ b/src/gui/windows/predictor/predictor_info_dock.cpp
@@ -91,7 +91,7 @@ DockPredictorInfo::DockPredictorInfo(QWidget *parent) : Super(parent) {
 
     // Stats
     label_stats_total_text->setText("Jump/Branch count:");
-    label_stats_miss_text->setText("Flush count:");
+    label_stats_miss_text->setText("Misprediction count:");
     label_stats_accuracy_text->setText("Total accuracy:");
     clear_stats();
 
@@ -223,6 +223,11 @@ void DockPredictorInfo::setup(
         value_bhr->setEnabled(false);
     }
 
+    if (number_of_bhr_bits == 0) {
+        label_bhr->setEnabled(false);
+        value_bhr->setEnabled(false);
+    }
+
     clear_bhr();
 }
 
diff --git a/src/machine/core.cpp b/src/machine/core.cpp
index f610cba1..c07cb797 100644
--- a/src/machine/core.cpp
+++ b/src/machine/core.cpp
@@ -532,6 +532,11 @@ MemoryState Core::memory(const ExecuteInterstage &dt) {
         }
     }
 
+    // Predictor statistics update
+    if (computed_next_inst_addr != dt.predicted_next_inst_addr) {
+        predictor->increment_mispredictions();
+    }
+
     return { MemoryInternalState {
                  .mem_read_val = towrite_val,
                  .mem_write_val = dt.val_rt,
@@ -721,11 +726,7 @@ void CorePipelined::handle_stall(const FetchInterstage &saved_if_id) {
 }
 
 bool CorePipelined::detect_mispredicted_jump() const {
-    bool misprediction = mem_wb.computed_next_inst_addr != mem_wb.predicted_next_inst_addr;
-    if (misprediction) {
-        predictor->increment_mispredictions();
-    }
-    return misprediction;
+    return mem_wb.computed_next_inst_addr != mem_wb.predicted_next_inst_addr;
 }
 
 bool CorePipelined::is_stall_requested() const {