This design combines a MicroBlaze CPU with a graphics frame buffer, and supports a variety of display resolutions from 640x480 to 1920x1080. The display colour depth is 24 bits (RGB).
Supported boards: Digilent Nexys Video and QMTECH Wukong.
The frame buffer is held in DDR3 SDRAM and the design uses a simple arbiter to share access to the DDR3 IP core’s user interface between the CPU and the display controller, with priority going to the display.
A simple MicroBlaze demo application is included, based on Mike Tuupola’s hagl graphics library.
Build the Vivado or Quartus project by running make in the relevant build directory, and program your board from the command line by running make prog. Once the project is built, you may use the IDE.
The diagram below shows the main design blocks:
The modules shown are described below:
- top
-
A board specific wrapper around the main design and the DDR3 controller IP core.
- mig
-
Board specific DDR3 controller IP core, produced by Xilinx Memory Interface Generator (MIG).
- mb_fb
-
Top level of main design.
- microblaze
-
A Xilinx Block Diagram - see the MicroBlaze CPU Subsystem section below for further details.
- mig_bridge_axi
-
Bridges from CPU’s AXI bus master to the the MIG user interface.
- crtc
-
Video clocking and timing control. The name is a throwback to the Cathode Ray Tube Controllers used in 80s and 90s era home computers.
- mig_bridge_crtc
-
Drives MIG user interface to fetch pixels from memory as required by CRTC.
- mig_hub
-
A priority arbiter to share access to the DDR3 controller’s user interface between multiple masters.
- dvi_tx
-
Contains TMDS encoders and serialisers to drive a DVI display monitor.
The MicroBlaze CPU is instantiated within a Xilinx Block Diagram file:
The blocks are described below:
- cpu
-
MicroBlaze CPU, 32 bit, microcontroller preset, no caches.
- ram
-
64kBytes for CPU instructions and data.
- interconnect
-
AXI interconnect to allow the CPU AXI master to connect to 3 AXI slaves.
- gpio
-
AXI GPIO IP core, configured for 2 channels: 8 outputs on the first channel, 8 inputs on the second.
- uart
-
"Lite" UART IP core, fixed at 115200N81, to provide console I/O (not used in this design).
- rstctrl
-
Reset controller IP core.
- debug
-
CPU debug controller IP core.
If you alter the block diagram in Vivado, you will need to export a TCL script to recreate by entering the following command in the TCL Console:
write_bd_tcl -force -include_layout ../../../src/designs/mb_fb/microblaze.tcl
To update the documentation, export an SVG image by entering the following command in the TCL Console:
write_bd_layout ‑force ‑format svg ../../../doc/designs/mb_fb/microblaze.svg
The application initialises the frame buffer and hagl library, draws 100 random graphical objects (lines, triangles, rectangles or ellipses), overlays this with a simple grid, and prints a message.
A simulation testbench is provided as part of the Vivado project. This captures the video output to a BMP file. Note that simulation run times are substantial. Alternative testbenches are provided to simulate simplified versions of the design that exclude the MIG; these run much faster.