03-dataflow_debug_and_optimization

Hardware Acceleration Tutorials See Vitis™ Development Environment on xilinx.com

Vitis HLS Analysis and Optimization

Version: Vitis 2023.2

Introduction

Vitis High-Level Synthesis (HLS) is a key part of the Vitis application acceleration development flow. The tool is responsible for compiling C/C++ and OpenCL code into a kernel for acceleration in the programmable logic (PL) region of AMD devices. Thus, it is the tool that compiles the hardware kernels for the Vitis tools by performing high-level synthesis.

The aim of this tutorial is to give you an overview of the techniques available in the Vitis HLS GUI with respect to understanding and debugging the dataflow optimization. You will be working through the AMD Vivado™ kernel flow in the Vitis tool. For more information, refer to Introduction to Vitis HLS Components in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).

IMPORTANT:

• Before running any of the examples, make sure you have installed the Vitis core development kit as described in Installation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
• If you run applications on the AMD Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions To complete installation, follow the instructions on the Alveo Product Documentation tab.

Accessing the Tutorial Reference Files

1. To access the reference files, type the following into a terminal: git clone https://github.com/Xilinx/Vitis-Tutorials.
2. Navigate to the Hardware_accelerators/Feature_Tutorials/03-dataflow_debug_and_optimization directory, and then access the reference-files directory.

Next Steps

Complete the labs in the following order:

1. Dataflow Viewer and the basics: Review how to launch the dataflow viewer and go over the various features.
2. FIFO Sizing and Deadlocks: Review how to use the deadlock detection feature in the GUI and how to resize FIFOs to avoid deadlocks and achieve better performance.

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