diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala
index 91af136cd3..5afe7e1d81 100644
--- a/src/main/scala/xiangshan/backend/CtrlBlock.scala
+++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala
@@ -257,7 +257,7 @@ class CtrlBlockImp(
     trace.io.in.fromPcMem(i) := pcMem.io.rdata(pcMemIdx).getPc(RegEnable(trace.toPcMem.blocks(i).bits.ftqOffset.get, traceValid))
   }
 
-  // Trap/Xret only occor in block(0).
+  // Trap/Xret only occur in block(0).
   val tracePriv = Mux(Itype.isTrapOrXret(trace.toEncoder.blocks(0).bits.tracePipe.itype),
     io.fromCSR.traceCSR.lastPriv,
     io.fromCSR.traceCSR.currentPriv
diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala b/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
index 51746ab5fa..790e275802 100644
--- a/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
@@ -228,13 +228,6 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
 
   val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak
 
-  // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN
-  val isXRetFlag = RegInit(false.B)
-  isXRetFlag := Mux1H(Seq(
-    DelayN(flush, 5) -> false.B,
-    isXRet -> true.B,
-  ))
-
   flushPipe := csrMod.io.out.bits.flushPipe
 
   // tlb
@@ -306,7 +299,7 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
   csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt
   csrOut.vpu.vxrm   := csrMod.io.status.vecState.vxrm.asUInt
 
-  csrOut.isXRet := RegEnable(isXRetFlag, false.B, io.in.fire)
+  csrOut.isXRet := isXRet
 
   csrOut.trapTarget := csrMod.io.out.bits.targetPc
   csrOut.interrupt := csrMod.io.status.interrupt
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
index 140d386d7d..4ef7252587 100644
--- a/src/main/scala/xiangshan/backend/rob/Rob.scala
+++ b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -1038,11 +1038,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
 
     // trace
     val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
-    val xret = csrWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === i.U && io.csr.isXRet).reduce(_ || _)
-
-    when(robEntries(i).valid && xret){
-      robEntries(i).traceBlockInPipe.itype := Itype.ExpIntReturn
-    }.elsewhen(robEntries(i).valid && Itype.isBranchType(robEntries(i).traceBlockInPipe.itype) && taken){
+    when(robEntries(i).valid && Itype.isBranchType(robEntries(i).traceBlockInPipe.itype) && taken){
       // BranchType code(notaken itype = 4) must be correctly replaced!
       robEntries(i).traceBlockInPipe.itype := Itype.Taken
     }
@@ -1106,10 +1102,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
 
     // trace
     val taken = branchWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && writeback.bits.redirect.get.bits.cfiUpdate.taken).reduce(_ || _)
-    val xret = csrWBs.map(writeback => writeback.valid && writeback.bits.robIdx.value === needUpdateRobIdx(i) && io.csr.isXRet).reduce(_ || _)
-    when(robBanksRdata(i).valid && xret){
-      needUpdate(i).traceBlockInPipe.itype := Itype.ExpIntReturn
-    }.elsewhen(robBanksRdata(i).valid && Itype.isBranchType(robBanksRdata(i).traceBlockInPipe.itype) && taken){
+    when(robBanksRdata(i).valid && Itype.isBranchType(robBanksRdata(i).traceBlockInPipe.itype) && taken){
       // BranchType code(notaken itype = 4) must be correctly replaced!
       needUpdate(i).traceBlockInPipe.itype := Itype.Taken
     }
@@ -1239,6 +1232,14 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   val traceBlocks = io.trace.traceCommitInfo.blocks
   val traceBlockInPipe = io.trace.traceCommitInfo.blocks.map(_.bits.tracePipe)
 
+  // The reg 'isTraceXret' only for trace xret instructions. xret only occur in block(0).
+  val isTraceXret = RegInit(false.B)
+  when(io.csr.isXRet){
+    isTraceXret := true.B
+  }.elsewhen(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){
+    isTraceXret := false.B
+  }
+
   for (i <- 0 until CommitWidth) {
     traceBlocks(i).bits.ftqIdx.foreach(_ := rawInfo(i).ftqIdx)
     traceBlocks(i).bits.ftqOffset.foreach(_ := rawInfo(i).ftqOffset)
@@ -1246,9 +1247,11 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
     traceBlockInPipe(i).iretire := rawInfo(i).traceBlockInPipe.iretire
     traceBlockInPipe(i).ilastsize := rawInfo(i).traceBlockInPipe.ilastsize
     traceValids(i) := io.commits.isCommit && io.commits.commitValid(i)
-    // exception only occor block(0).
+    // exception/xret only occur in block(0).
     if(i == 0) {
-      when(io.exception.valid){
+      when(isTraceXret && io.commits.isCommit && io.commits.commitValid(0)){ // trace xret
+        traceBlocks(i).bits.tracePipe.itype := Itype.ExpIntReturn
+      }.elsewhen(io.exception.valid){ // trace exception
         traceBlocks(i).bits.tracePipe.itype := Mux(io.exception.bits.isInterrupt,
           Itype.Interrupt,
           Itype.Exception