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Bug in axis_sim_stim.vhd file #3

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Vic0428 opened this issue Jan 17, 2022 · 1 comment
Open

Bug in axis_sim_stim.vhd file #3

Vic0428 opened this issue Jan 17, 2022 · 1 comment

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@Vic0428
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Vic0428 commented Jan 17, 2022

Hi all,

Thanks for your great work and I really love NetFPGA project!

I found there maybe one bug in the axis_sim_stim.vhd file. It handles @(N) as same as +(N) and doesn't provide the semantic of wait until some absolute time.

            -- operator @(N): wait until absolute time N ns
            	elsif c = '@' then          -- wait until absolute time (ns)              
		    read_char( l, c );      -- discard operator
         	    parse_int( l, i );
            	    quiescent;
		    wait for ( i * 1 ns);
                    wait_cycle;

            -- operator +(N): wait for N ns
            	elsif c = '+' then          -- wait for relative time (ns)
               	    read_char( l, c );      -- discard operator
                    parse_int( l, i );
                    quiescent;
		    wait for ( i * 1 ns);                
                    wait_cycle;

Have a nice day!

Thanks,
Vic

@aomtoku
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aomtoku commented Aug 26, 2023

Hi @Vic0428 , Thank you for pointing out this. I will check this.

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