Setup Verilator for multiple clock domain simulations

[JulianKemmerer]

• Requires a VHDL async "AXIS style FWFT" fifo implementation to use
  • Real hardware uses manufacturer macros
  • Previously took sync Verilog fifo and used that
• Simulation should ideally generate clocks in the HDL
  • Ugh oh - how to get that through yosys for write_verilog?
  • GHDL for VHDL to Verilog has duplicate wire issue so can't use that yet