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Wishlist: proposed features
Jesús Arroyo Torrens edited this page Dec 23, 2016
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Execute Icestudio as a client, on a remote server. Instead of "apio build" execute "192.168.0.1 / apio build"
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Generation of test-benches (export generic testbenches)(proposed by Carlos Santiago Díaz)
Standalone packagingShow examples for the selected boardAdd boards documentation-
Detect system language (https://github.com/Elzair/node-lang-info)(Proposed by Salvador) Option for Showing the Resources availables / used when synthetising a circuit (It will be necessary to parse the output generated by Arachne)-
Close error notifications only on click(Proposed by AlexTC) -
View selected board in the panel(Proposed by AlexTC) -
Manage the wires that are connected, placing a dot en the union. Sometimes is hard to visualize if two wires that cross are or not connected(Proposed by Jose Javier Jimenez Viton)
Block-code with user-defined parameters (Ex. number of bits of the divisor). When the block is placed, also the parameter can be set-
Use Constant blocks for parameters(Proposed by Salvador) When exporting a block, the ordination or the outputs should be taken from the y-coordinate. Now it is taken from the ordination of creation of the pin. It is more clear if the ordination is taken from the original blockAdd "Project information" section: name, version, description, author, imageInclude compressed SVG image in the projectUpdate Project formatAdd "Add project as block" option: remove ".iceb" concept, only ".ice" will be usedPort created as virtual (green), then they can be converted into FPGA I/O ports (yellow)Use N-bit wires- Tooltip with a block description (Proposed by Carlos Santiago Díaz)
- Add boards photos information (Proposed by Salvador)
- Notification: save current project before new project
- Detect project modifications
- Add
Don't ask "remove block" again
option
- Simulation with GTKwave (Proposed by Carlos Santiago Díaz)
- Serial terminal integrated in Icestudio
- Generation of Finite state machines (Proposed by Carlos Santiago Díaz)
- Test with Electron
- Parametrized blocks
- Iterative block edition
- Refactor all graphics: jointjs has behavior problems with SVG, HTML elements, Mouse events and zIndexes.
- Import modules with write access. Currently, when a module is imported into a project, you can only see the code, but cannot change anything. After using icestudio with real project, I think (obijuan) that it would be better if the modules can be changed inside the project. I really do not know if this is easy or hard to implement. The changes should only happen in the module edited. If there are many instances of a module, only the one instance is changed
- Option for update the modules. If you want to include a new updated version of a module, which have many instances in the current project, it would be great to have an option for doing that (all the modules updated)
- Blocks/Examples/Templates manager.
- Edit FPGA I/O pin by number (Proposed by Democrito)
- Colored wires (Proposed by Democrito)
- Undo/Redo (Proposed by AlexTC)
- Add labels to wires (Proposed by tonicobi)
- Default: Icestudio Default Collection
- IceK: Constants
- IceWires: Wires and Buses
- IceIO: FPGA IO-pins
- IceGates: Logic gates
- IceMux: Muxes and demuxes
- IceCoders: Binary Encoders and Decoders
- IceFF: Flip-Flops
- IceRegs: Registers
- IceSRegs: Shift Registers
- IceBoards: blocks and examples for the diferent FPGA boards
- IceComp: Comparators
- IceArith: Integer arithmetics
- IceCounter: Counters
- IceSignals: 1-bit signal managment
- IcePLL: PLLs
- IceLEDOscope: Measuring signals
- IceLEDs: Displaying on LEDs
- IceHearts: Timming signal generation
- IceInputs: 1-bit inputs
- IceRok: Block probes for Icestudio => Sigrok integration (with Pulseview GUI)
- IceMachines: Working with Machines (simple state machines with a standar interface)
- IceSerial: Serial Asynchronous communications
- IceMem: Working with Memories
- IceMeasure: Measuring cycles and time in your circuits, very easily
- IceStack: Working with stacks
- IceFlash: Read from spi serial flash memories
- IceBus: Accesing and sharing simple buses
- IceLCD: Components and controllers for LCDs
- IceUnary: Working with unary numbers
- IceCrystal: Drive displays from Open Source FPGAs
- ice-chips-verilog: IceChips is a library of all common discrete logic devices in Verilog
- ArithmeticBlocks: FPGA signed and unsigned integer operations, 16, 24 and 32 bits, + - * / sqrt min max compare etc.
- iceSynth: Audio synthesis
- icebreaker: Blocks and examples for the icebreaker OpenFPGA board
- Jedi: blocks of the FPGA Jedi hardware Academy
- LOVE-FPGA: Hardware elements and examples for the LOVE-FPGA project (Linking Of Virtual Electronics to FPGAs)
- Stdio: Standard Input-Output in different devices
- CT11: Ejemplos del cuaderno ténico 11: Señales del sistema y Medición con el LEDOscopio
- Generic: Icestudio Generic Collection
- Logic: Icestudio Logic Collection
- IceInterface: Serial, SPI, I2C... (TODO)
- IceK-TB: Tests for iceK
- IceWires-TB: Test for icewires
- IceIO-TB: Tests for iceIO
- iceGates-TB: Tests for gates
- iceCoders-TB: Tests for iceCoders
- IceFF-TB: Tests for iceFF
- IceRegs-TB: Tests for registers
- IceSregs-TB: Tests for shift registers
- Jedi-Test: Tests for the blocks on the Jedi Collection