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testlist_allactive.xml
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testlist_allactive.xml
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<?xml version="1.0"?>
<testlist version="2.0">
<test name="ERI" grid="f09_g17" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERI" grid="f09_g17" compset="B1850Ws" testmods="allactive/default">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERI" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERR" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="NCK" grid="f19_g17" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 02:00 </option>
</options>
</test>
<test name="NCK" grid="f19_g17" compset="B1850Ws" testmods="allactive/defaultiomi">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 02:00 </option>
</options>
</test>
<test name="ERS_D" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 06:00 </option>
</options>
</test>
<test name="IRT" grid="f19_g17" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="IRT" grid="f09_g17" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prealpha"/>
<machine name="edison" compiler="cray" category="prealpha"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="ERS" grid="f19_g17" compset="B1850Ws" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:25 </option>
</options>
</test>
<test name="IRT" grid="f09_g17" compset="BRCP85L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="ERS_Ld7" grid="ne30_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="IRT_Ld7" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_Ld1" grid="f09_g17" compset="BW1850" testmods="allactive/default">
<machines>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="bwaccm"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f19_g17" compset="BWma1850" testmods="allactive/default">
<machines>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="bwaccm"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="IRT_Ld7" grid="T31_g37" compset="B1850L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:00 </option>
</options>
</test>
<test name="ERS_Ld5" grid="f19_g17" compset="E1850L45TEST" testmods="cice/default">
<machines>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="ERS_Ld7" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
<machine name="hobart" compiler="pgi" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="IRT_Ld7" grid="ne30_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="gnu" category="prealpha"/>
<machine name="cheyenne" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="ERS_Ld7" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="ERS_Ld9" grid="ne120_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="IRT_N3_PM3_Ld7" grid="f19_g17" compset="BHISTWs" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
<machine name="cheyenne" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 02:00 </option>
</options>
</test>
<test name="ERS_Ld7" grid="f09_g17" compset="BRCP85L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="NCK_Ld5" grid="f19_g17" compset="BC5L45BGCR" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="NCK_Ld5" grid="f19_g17" compset="B1850GWs" testmods="allactive/cism/test_coupling">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 01:30 </option>
<option name="comment">Needs to be B1850GWs rather than B1850G because WW3 currently does not support multi-instance</option>
</options>
</test>
<test name="PET_PM" grid="f19_g17" compset="B1850" testmods="allactive/defaultiomi">
<machines>
<machine name="cheyenne" compiler="gnu" category="prealpha"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 01:30 </option>
</options>
</test>
<test name="PET" grid="ne30_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="PFS" grid="f09_g17" compset="B1850" testmods="allactive/default">
<machines>
<machine name="bluewaters" compiler="pgi" category="prebeta"/>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="PFS" grid="f09_g17" compset="B1850" testmods="allactive/default">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test name="PFS" grid="f09_g17" compset="B1850" testmods="allactive/maxthroughputb">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_perf"/>
</machines>
<options>
<option name="wallclock"> 00:40 </option>
</options>
</test>
<test compset="FW1850" grid="f09_f09_mg17" name="PFS" testmods="allactive/maxthroughputfw">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_perf"/>
</machines>
</test>
<test name="PFS" grid="ne30_g17" compset="B1850" testmods="allactive/default">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_D" grid="f19_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_D" grid="f09_g17" compset="BHIST" testmods="allactive/defaultio">
<machines>
<machine name="edison" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f19_g17" compset="B1850G" testmods="allactive/cism/test_coupling">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f09_g17" compset="B1850G" testmods="allactive/cism/test_coupling">
<machines>
<machine name="cheyenne" compiler="intel" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f19_g17" compset="B1850G1" testmods="allactive/cism/test_coupling">
<machines>
<machine name="cheyenne" compiler="gnu" category="prebeta">
<options>
<option name="wallclock">0:30</option>
<option name="comment">Include a fully-coupled test with CISM1, mainly to make sure the PE layout works</option>
</options>
</machine>
</machines>
</test>
<test name="SMS_Ld1" grid="f19_g17" compset="B1850G" testmods="allactive/cism/test_coupling">
<machines>
<machine name="hobart" compiler="nag" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:45 </option>
</options>
</test>
<test name="SMS_Ld5" grid="f09_g17_gl4" compset="J1850G" testmods="allactive/cism/test_coupling">
<machines>
<machine name="cheyenne" compiler="gnu" category="prebeta"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
<test name="SMS_Ld7" grid="f09_g17" compset="B1850" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha"/>
</machines>
<options>
<option name="wallclock"> 00:30 </option>
</options>
</test>
</testlist>