From e25b58a4e8053fd08c7313d47626db9875c1e719 Mon Sep 17 00:00:00 2001 From: a-ramses Date: Fri, 13 Dec 2024 01:18:43 +0100 Subject: [PATCH 1/6] Add support for retrieving boot cpu and mpidr for M3+ Signed-off-by: a-ramses --- proxyclient/experiments/cpu_pstate_latencies.py | 3 ++- proxyclient/m1n1/proxy.py | 6 ++++++ src/proxy.c | 6 ++++++ src/proxy.h | 2 ++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/proxyclient/experiments/cpu_pstate_latencies.py b/proxyclient/experiments/cpu_pstate_latencies.py index 490c09d9e..601550bc3 100755 --- a/proxyclient/experiments/cpu_pstate_latencies.py +++ b/proxyclient/experiments/cpu_pstate_latencies.py @@ -88,7 +88,8 @@ p.ic_ivau(code, len(util.data)) def bench_cpu(idx, loops=10000000): - if idx == 0: + boot_cpu_name = "cpu" + str(p.get_boot_cpu_idx()) + if (cpu + idx) == boot_cpu_name: elapsed = p.call(util.bench, loops) / tfreq else: elapsed = p.smp_call_sync(idx, util.bench, loops) / tfreq diff --git a/proxyclient/m1n1/proxy.py b/proxyclient/m1n1/proxy.py index 9a89fb61f..92447a8eb 100644 --- a/proxyclient/m1n1/proxy.py +++ b/proxyclient/m1n1/proxy.py @@ -495,6 +495,8 @@ class M1N1Proxy(Reloadable): P_REBOOT = 0x010 P_SLEEP = 0x011 P_EL3_CALL = 0x012 + P_GET_BOOT_CPU_IDX = 0x013 + P_GET_BOOT_CPU_MPIDR = 0x014 P_WRITE64 = 0x100 P_WRITE32 = 0x101 @@ -725,6 +727,10 @@ def get_bootargs_rev(self): ba_addr = self.request(self.P_GET_BOOTARGS) rev = self.read16(ba_addr) return (ba_addr, rev) + def get_boot_cpu_idx(self): + return self.request(self.P_GET_BOOT_CPU_IDX) + def get_boot_cpu_mpidr(self): + return self.request(self.P_GET_BOOT_CPU_MPIDR) def get_base(self): return self.request(self.P_GET_BASE) def set_baud(self, baudrate): diff --git a/src/proxy.c b/src/proxy.c index c59225ca2..6cdff7ad8 100644 --- a/src/proxy.c +++ b/src/proxy.c @@ -54,6 +54,12 @@ int proxy_process(ProxyRequest *request, ProxyReply *reply) case P_GET_BOOTARGS: reply->retval = boot_args_addr; break; + case P_GET_BOOT_CPU_IDX: + reply->retval = boot_cpu_idx; + break; + case P_GET_BOOT_CPU_MPIDR: + reply->retval = boot_cpu_mpidr; + break; case P_GET_BASE: reply->retval = (u64)_base; break; diff --git a/src/proxy.h b/src/proxy.h index 34c419eed..e1f0ef4ad 100644 --- a/src/proxy.h +++ b/src/proxy.h @@ -25,6 +25,8 @@ typedef enum { P_REBOOT, P_SLEEP, P_EL3_CALL, + P_GET_BOOT_CPU_IDX, + P_GET_BOOT_CPU_MPIDR, P_WRITE64 = 0x100, // Generic register functions P_WRITE32, From a4124668fb173b2ff4eb8e66a8176d70cf5bb296 Mon Sep 17 00:00:00 2001 From: a-ramses Date: Fri, 13 Dec 2024 01:30:12 +0100 Subject: [PATCH 2/6] chickens: Initial T6030 Everest/Sawtooth support Signed-off-by: a-ramses --- src/chickens.c | 14 ++++++++++++++ src/chickens_everest.c | 43 +++++++++++++++++++++++++++++++++++++++++ src/chickens_sawtooth.c | 13 +++++++++++++ src/cpu_regs.h | 2 ++ src/soc.h | 3 +++ 5 files changed, 75 insertions(+) diff --git a/src/chickens.c b/src/chickens.c index da132b7fc..4e9525cc8 100644 --- a/src/chickens.c +++ b/src/chickens.c @@ -39,6 +39,8 @@ #define MIDR_PART_T6020_AVALANCHE 0x35 #define MIDR_PART_T6021_BLIZZARD 0x38 #define MIDR_PART_T6021_AVALANCHE 0x39 +#define MIDR_PART_T6030_SAWTOOTH 0x44 +#define MIDR_PART_T6030_EVEREST 0x45 #define MIDR_PART_T6031_EVEREST 0x49 #define MIDR_PART_T6031_SAWTOOTH 0x48 @@ -66,6 +68,8 @@ void init_t6020_blizzard(void); void init_t6020_avalanche(int rev); void init_t6021_blizzard(void); void init_t6021_avalanche(int rev); +void init_t6030_sawtooth(void); +void init_t6030_everest(int rev); void init_t6031_sawtooth(void); void init_t6031_everest(int rev); @@ -204,6 +208,16 @@ const char *init_cpu(void) init_t6021_blizzard(); break; + case MIDR_PART_T6030_EVEREST: + cpu = "M3 Pro Everest"; + init_t6030_everest(rev); + break; + + case MIDR_PART_T6030_SAWTOOTH: + cpu = "M3 Pro Sawtooth"; + init_t6030_sawtooth(); + break; + case MIDR_PART_T6031_EVEREST: cpu = "M3 Max Everest"; init_t6031_everest(rev); diff --git a/src/chickens_everest.c b/src/chickens_everest.c index cab8faea1..4ed20cf8c 100644 --- a/src/chickens_everest.c +++ b/src/chickens_everest.c @@ -36,6 +36,49 @@ static void init_common_everest(void) reg_clr(s3_0_c15_c2_4, BIT(0) | BIT(1) | BIT(16) | BIT(17) | BIT(18) | BIT(22)); } +void init_t6030_everest(int rev) +{ + UNUSED(rev); + msr(s3_1_c15_c1_5, 0x1uL); + if (in_el2()) + msr(s3_4_c15_c14_6, 0x3uL); + + reg_set(SYS_IMP_APL_HID16, BIT(54)); + reg_set(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE); + reg_mask(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_LIMIT_MASK, HID3_DEV_PCIE_THROTTLE_LIMIT(60)); + reg_clr(SYS_IMP_APL_HID3, BIT(4)); + reg_set(SYS_IMP_APL_HID9, BIT(17)); + reg_mask(SYS_IMP_APL_HID13, + HID13_POST_OFF_CYCLES_MASK | HID13_POST_ON_CYCLES_MASK | + HID13_PRE_CYCLES_MASK | HID13_GROUP0_FF0_DELAY_MASK | + HID13_GROUP0_FF1_DELAY_MASK | HID13_GROUP0_FF2_DELAY_MASK | + HID13_GROUP0_FF3_DELAY_MASK | HID13_GROUP0_FF4_DELAY_MASK | + HID13_GROUP0_FF5_DELAY_MASK | HID13_GROUP0_FF6_DELAY_MASK | + HID13_GROUP0_FF7_DELAY_MASK | HID13_RESET_CYCLES_MASK, + HID13_POST_OFF_CYCLES(4) | HID13_POST_ON_CYCLES(5) | HID13_PRE_CYCLES(1) | HID13_GROUP0_FF0_DELAY(0) | + HID13_GROUP0_FF1_DELAY(4) | HID13_GROUP0_FF2_DELAY(4) | HID13_GROUP0_FF3_DELAY(4) | + HID13_GROUP0_FF4_DELAY(4) | HID13_GROUP0_FF5_DELAY(4) | HID13_GROUP0_FF6_DELAY(4) | + HID13_GROUP0_FF7_DELAY(4) | HID13_RESET_CYCLES(0)); + + msr(SYS_IMP_APL_HID26, + HID26_GROUP1_OFFSET(0x16 | (0x2 << 8) | (0x2 << 12) | (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28) | (0x2uL << 32)) | + HID26_GROUP2_OFFSET(0x23 | (0x1 << 8) | (0x1 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24))); + + reg_mask(SYS_IMP_APL_HID27, + GENMASK(43, 40) | GENMASK(39, 36) | GENMASK(35, 32) | GENMASK(31, 28) | + GENMASK(27, 24) | GENMASK(23, 20) | GENMASK(19, 16) | GENMASK(15, 8) | + GENMASK(7, 4) | GENMASK(3, 0), + BIT(40) | BIT(36) | BIT(32) | BIT(28) | BIT(24) | BIT(20) | BIT(16) | 0x2b00uL | + BIT(4) | BIT(0)); + + reg_set(SYS_IMP_APL_HID18, BIT(61) | HID18_GENTER_SPECULATION_DISABLE | HID18_GEXIT_EL_SPECULATION_DISABLE); + + reg_set(s3_0_c15_c2_3, BIT(3)); + reg_clr(s3_0_c15_c2_4, BIT(0) | BIT(1) | BIT(16) | BIT(17) | BIT(18) | BIT(22)); + + reg_set(SYS_IMP_APL_HID4, HID4_ENABLE_LFSR_STALL_LOAD_PIPE2_ISSUE); +} + void init_t6031_everest(int rev) { UNUSED(rev); diff --git a/src/chickens_sawtooth.c b/src/chickens_sawtooth.c index 8e9fe317e..9a263348a 100644 --- a/src/chickens_sawtooth.c +++ b/src/chickens_sawtooth.c @@ -8,6 +8,19 @@ static void init_common_sawtooth(void) reg_set(SYS_IMP_APL_EHID0, EHID0_BLI_UNK32); } +void init_t6030_sawtooth(void) +{ + // disable CNTFREQ scaling 1GHz + msr(s3_1_c15_c1_5, 0x3uL); + init_common_sawtooth(); + reg_mask(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_LIMIT_MASK, EHID9_DEV_2_THROTTLE_LIMIT(62)); + reg_set(SYS_IMP_APL_EHID9, EHID9_DEV_2_THROTTLE_ENABLE); + + reg_set(SYS_IMP_APL_EHID18, EHID18_BLZ_UNK34); + + reg_mask(SYS_IMP_APL_HID5, HID5_BLZ_UNK_19_18_MASK, HID5_BLZ_UNK19); +} + void init_t6031_sawtooth(void) { init_common_sawtooth(); diff --git a/src/cpu_regs.h b/src/cpu_regs.h index 9fe3b9cdf..ef941b366 100644 --- a/src/cpu_regs.h +++ b/src/cpu_regs.h @@ -339,6 +339,8 @@ #define HID13_POST_ON_CYCLES_MASK GENMASK(13, 7) #define HID13_PRE_CYCLES(x) ((ULONG(x)) << 14) #define HID13_PRE_CYCLES_MASK GENMASK(17, 14) +#define HID13_GROUP0_FF0_DELAY(x) ((ULONG(x)) << 18) +#define HID13_GROUP0_FF0_DELAY_MASK GENMASK(25, 18) #define HID13_GROUP0_FF1_DELAY(x) ((ULONG(x)) << 26) #define HID13_GROUP0_FF1_DELAY_MASK GENMASK(29, 26) #define HID13_GROUP0_FF2_DELAY(x) ((ULONG(x)) << 30) diff --git a/src/soc.h b/src/soc.h index b6632ad2d..dfd9d894f 100644 --- a/src/soc.h +++ b/src/soc.h @@ -25,6 +25,7 @@ #define T6020 0x6020 #define T6021 0x6021 #define T6022 0x6022 +#define T6030 0x6030 #define T6031 0x6031 #define T6034 0x6034 @@ -41,6 +42,8 @@ #define EARLY_UART_BASE 0x391200000 #elif TARGET == T8015 #define EARLY_UART_BASE 0x22e600000 +#elif TARGET == T6030 +#define EARLY_UART_BASE 0x289200000 #elif TARGET == T7000 || TARGET == T7001 || TARGET == S8000 || TARGET == S8001 || \ TARGET == S8003 || TARGET == T8010 || TARGET == T8011 #if TARGET == T7000 && defined(TARGET_BOARD) && TARGET_BOARD == 0x34 // Apple TV HD From 093efd265f77dbc2fcb34ff4009d3e9733ff7585 Mon Sep 17 00:00:00 2001 From: a-ramses Date: Fri, 13 Dec 2024 01:32:09 +0100 Subject: [PATCH 3/6] cpufreq: Initial T6030 support apsc cannot be initialized using bit 40 on the PCPU cluster without triggering an SError but can be set on ECPU Signed-off-by: a-ramses --- src/cpufreq.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/cpufreq.c b/src/cpufreq.c index 7dd33b2e2..3940a1be4 100644 --- a/src/cpufreq.c +++ b/src/cpufreq.c @@ -200,6 +200,13 @@ static const struct cluster_t t6031_clusters[] = { {"PCPU1", 0x212e00000, true, 1, 6}, {}, }; + +static const struct cluster_t t6030_clusters[] = { + {"ECPU0", 0x210e00000, false, 1, 5}, + {"PCPU0", 0x211e00000, true, 1, 6}, + {}, +}; + const struct cluster_t *cpufreq_get_clusters(void) { switch (chip_id) { @@ -217,6 +224,8 @@ const struct cluster_t *cpufreq_get_clusters(void) return t6020_clusters; case T6022: return t6022_clusters; + case T6030: + return t6030_clusters; case T6031: return t6031_clusters; default: @@ -268,6 +277,18 @@ static const struct feat_t t6031_features[] = { {}, }; +static const struct feat_t t6030_features[] = { + {"cpu-apsc", CLUSTER_PSTATE, CLUSTER_PSTATE_M2_APSC_DIS, 0, CLUSTER_PSTATE_APSC_BUSY, false}, + {"ppt-thrtl", 0x48400, 0, BIT(63), 0, false}, + {"ppt-thrtl", 0x48408, 0, BIT(63), 0, false}, + {"llc-thrtl", 0x40270, 0, BIT(63), 0, false}, + {"amx-thrtl", 0x40250, 0, BIT(63), 0, false}, + {"cpu-fixed-freq-pll-relock", CLUSTER_PSTATE, 0, CLUSTER_PSTATE_FIXED_FREQ_PLL_RECLOCK, 0, + false}, + {}, +}; + + const struct feat_t *cpufreq_get_features(void) { switch (chip_id) { @@ -280,6 +301,8 @@ const struct feat_t *cpufreq_get_features(void) case T6021: case T6022: return t6020_features; + case T6030: + return t6030_features; case T6031: return t6031_features; default: From 22a8e14b14ba3c2ef04627cbb59d38861969e789 Mon Sep 17 00:00:00 2001 From: a-ramses Date: Fri, 13 Dec 2024 01:43:06 +0100 Subject: [PATCH 4/6] smp: T6030 cpu start offset Signed-off-by: a-ramses --- proxyclient/m1n1/hv/__init__.py | 2 +- src/smp.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/proxyclient/m1n1/hv/__init__.py b/proxyclient/m1n1/hv/__init__.py index 1f223d97b..6219484d9 100644 --- a/proxyclient/m1n1/hv/__init__.py +++ b/proxyclient/m1n1/hv/__init__.py @@ -1562,7 +1562,7 @@ def cpustart_wh(base, off, data, width): chip_id = self.u.adt["/chosen"].chip_id if chip_id in (0x8103, 0x6000, 0x6001, 0x6002): cpu_start = 0x54000 + die * 0x20_0000_0000 - elif chip_id in (0x8112, 0x8122): + elif chip_id in (0x8112, 0x8122, 0x6030): cpu_start = 0x34000 + die * 0x20_0000_0000 elif chip_id in (0x6020, 0x6021, 0x6022): cpu_start = 0x28000 + die * 0x20_0000_0000 diff --git a/src/smp.c b/src/smp.c index 15ccc0e40..8059159d0 100644 --- a/src/smp.c +++ b/src/smp.c @@ -18,6 +18,7 @@ #define CPU_START_OFF_T8103 0x54000 #define CPU_START_OFF_T8112 0x34000 #define CPU_START_OFF_T6020 0x28000 +#define CPU_START_OFF_T6030 0x34000 #define CPU_START_OFF_T6031 0x88000 #define CPU_REG_CORE GENMASK(7, 0) @@ -279,6 +280,9 @@ void smp_start_secondaries(void) case T6022: cpu_start_off = CPU_START_OFF_T6020; break; + case T6030: + cpu_start_off = CPU_START_OFF_T6030; + break; case T6031: case T6034: cpu_start_off = CPU_START_OFF_T6031; From 6ab85eea57a43f04d75c85109d7f97e205e9a71e Mon Sep 17 00:00:00 2001 From: a-ramses Date: Fri, 13 Dec 2024 01:44:30 +0100 Subject: [PATCH 5/6] add removal of hpm devices on new device manager Signed-off-by: a-ramses --- proxyclient/m1n1/hv/__init__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/proxyclient/m1n1/hv/__init__.py b/proxyclient/m1n1/hv/__init__.py index 6219484d9..24577c49e 100644 --- a/proxyclient/m1n1/hv/__init__.py +++ b/proxyclient/m1n1/hv/__init__.py @@ -1612,6 +1612,7 @@ def setup_adt(self): "/arm-io/dart-apciec%d", "/arm-io/apciec%d-piodma", "/arm-io/i2c0/hpmBusManager/hpm%d", + "/arm-io/nub-spmi-a0/hpm%d", "/arm-io/atc%d-dpxbar", "/arm-io/atc%d-dpphy", "/arm-io/atc%d-dpin0", From 5e7a5cf3ba32fafe67bb42c6d0bc67a54f9f2a92 Mon Sep 17 00:00:00 2001 From: a-ramses <89321408+a-ramses@users.noreply.github.com> Date: Fri, 13 Dec 2024 13:56:57 +0100 Subject: [PATCH 6/6] clang format fix --- src/chickens_everest.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/chickens_everest.c b/src/chickens_everest.c index 4ed20cf8c..22a07aebf 100644 --- a/src/chickens_everest.c +++ b/src/chickens_everest.c @@ -49,21 +49,22 @@ void init_t6030_everest(int rev) reg_clr(SYS_IMP_APL_HID3, BIT(4)); reg_set(SYS_IMP_APL_HID9, BIT(17)); reg_mask(SYS_IMP_APL_HID13, - HID13_POST_OFF_CYCLES_MASK | HID13_POST_ON_CYCLES_MASK | - HID13_PRE_CYCLES_MASK | HID13_GROUP0_FF0_DELAY_MASK | - HID13_GROUP0_FF1_DELAY_MASK | HID13_GROUP0_FF2_DELAY_MASK | - HID13_GROUP0_FF3_DELAY_MASK | HID13_GROUP0_FF4_DELAY_MASK | - HID13_GROUP0_FF5_DELAY_MASK | HID13_GROUP0_FF6_DELAY_MASK | - HID13_GROUP0_FF7_DELAY_MASK | HID13_RESET_CYCLES_MASK, - HID13_POST_OFF_CYCLES(4) | HID13_POST_ON_CYCLES(5) | HID13_PRE_CYCLES(1) | HID13_GROUP0_FF0_DELAY(0) | - HID13_GROUP0_FF1_DELAY(4) | HID13_GROUP0_FF2_DELAY(4) | HID13_GROUP0_FF3_DELAY(4) | - HID13_GROUP0_FF4_DELAY(4) | HID13_GROUP0_FF5_DELAY(4) | HID13_GROUP0_FF6_DELAY(4) | - HID13_GROUP0_FF7_DELAY(4) | HID13_RESET_CYCLES(0)); + HID13_POST_OFF_CYCLES_MASK | HID13_POST_ON_CYCLES_MASK | HID13_PRE_CYCLES_MASK | + HID13_GROUP0_FF0_DELAY_MASK | HID13_GROUP0_FF1_DELAY_MASK | + HID13_GROUP0_FF2_DELAY_MASK | HID13_GROUP0_FF3_DELAY_MASK | + HID13_GROUP0_FF4_DELAY_MASK | HID13_GROUP0_FF5_DELAY_MASK | + HID13_GROUP0_FF6_DELAY_MASK | HID13_GROUP0_FF7_DELAY_MASK | + HID13_RESET_CYCLES_MASK, + HID13_POST_OFF_CYCLES(4) | HID13_POST_ON_CYCLES(5) | HID13_PRE_CYCLES(1) | + HID13_GROUP0_FF0_DELAY(0) | HID13_GROUP0_FF1_DELAY(4) | HID13_GROUP0_FF2_DELAY(4) | + HID13_GROUP0_FF3_DELAY(4) | HID13_GROUP0_FF4_DELAY(4) | HID13_GROUP0_FF5_DELAY(4) | + HID13_GROUP0_FF6_DELAY(4) | HID13_GROUP0_FF7_DELAY(4) | HID13_RESET_CYCLES(0)) msr(SYS_IMP_APL_HID26, - HID26_GROUP1_OFFSET(0x16 | (0x2 << 8) | (0x2 << 12) | (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28) | (0x2uL << 32)) | - HID26_GROUP2_OFFSET(0x23 | (0x1 << 8) | (0x1 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24))); - + HID26_GROUP1_OFFSET(0x16 | (0x2 << 8) | (0x2 << 12) | (0x2 << 16) | (0x2 << 20) | + (0x2 << 24) | (0x2 << 28) | (0x2uL << 32)) | + HID26_GROUP2_OFFSET(0x23 | (0x1 << 8) | (0x1 << 12) | (0x1 << 16) | (0x1 << 20) | + (0x1 << 24))); reg_mask(SYS_IMP_APL_HID27, GENMASK(43, 40) | GENMASK(39, 36) | GENMASK(35, 32) | GENMASK(31, 28) | GENMASK(27, 24) | GENMASK(23, 20) | GENMASK(19, 16) | GENMASK(15, 8) |