POST code capture and display in Daytona CRB

[ramakrishnan-vepl]

Hi,

we are developing openBMC port for the Daytona platform with ATS 2500 BMC. I need the following functionality to be implemented.

1. Capture of the LSB of the 32-bit post code and lit 8 LEDs on the GPIOAA port by configuring SNPWADR with one address of 0x0080 and directing the data to the GPIO port pins GPIOAA[7:0].

2. Also read and store the 32-bit Post code as 4 bytes from the the LPC I/O write cycles directed to Port address 0x0080 , 0x0081, 0x0082 and 0x0083 in the root file system for every power cycle and later display on the web GUI by Configuring post code control register PCCR0-3 for DMA/FIFO mode.

Could you please let us know if implementation for the above said two is available in openBMC community else suggest implementation pointers.

Regards,
Ramakrishnan